Timeline for FPGA SPI slave doesn't work if driving it with the fast FPGA clock instead of with the SPI master clock (oversampling)
Current License: CC BY-SA 4.0
11 events
| when toggle format | what | by | license | comment | |
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| Nov 22, 2021 at 11:26 | history | edited | Martel | CC BY-SA 4.0 |
deleted 8 characters in body
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| Nov 22, 2021 at 9:43 | vote | accept | Martel | ||
| Nov 21, 2021 at 13:05 | answer | added | awjlogan | timeline score: 1 | |
| Nov 19, 2021 at 21:06 | comment | added | Martel |
@awjlogan I tried it, passing slave_recv_data_rdy through a pos_edge_detector. I get the same result
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| Nov 19, 2021 at 20:36 | comment | added | awjlogan |
I'm suspicious of your @(posedge slave_recv_data_rdy) block - usually edge sensitivity is done on a clock. You can use the clock edge, and if (slave_recv_data_rdy) begin....
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| Nov 19, 2021 at 19:06 | comment | added | Martel | @TomCarpenter that can't be because, as explained, if I route the master clock to the slave directly, everything works fine. | |
| Nov 19, 2021 at 19:05 | comment | added | Tom Carpenter | If it works in simulation, could it be something as simple as your LEDs being active low (i.e. a 0 turns the LED on)? | |
| Nov 19, 2021 at 19:00 | comment | added | Martel | Yes, I have simulated it with a master implemented by me as well. Everything works, I can provide the GTKWave caputre. | |
| Nov 19, 2021 at 18:59 | comment | added | Mitu Raj | So did you simulate this with any spi master before proceeding to on-board testing? | |
| Nov 19, 2021 at 18:55 | comment | added | jay | I can come back later, if you don't get any help, please let me know. It seems like you are from C side. I like the __macro style in hdl, haven't thought to do that. Meantime, I noticed "always @ (posedge clk or posedge prst) begin". From my far distance memory, something did not like clocked by logic, and it may consume large amount of the resources. | |
| Nov 19, 2021 at 18:12 | history | asked | Martel | CC BY-SA 4.0 |