Timeline for Basic memory element circuit
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Dec 19, 2021 at 2:00 | history | edited | JYelton | CC BY-SA 4.0 |
added 4 characters in body; edited title
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| Dec 18, 2021 at 16:25 | comment | added | Elliot Alderson | To make this a working circuit you need to ensure that the drive strength of the right inverter is much weaker than the strength of whatever is connected to the latch's D input (the input of the left inverter). | |
| Dec 18, 2021 at 15:39 | history | edited | JRE | CC BY-SA 4.0 |
deleted 34 characters in body; edited title
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| Dec 18, 2021 at 14:35 | answer | added | devnull | timeline score: 1 | |
| Dec 18, 2021 at 14:16 | answer | added | Jonathan S. | timeline score: 0 | |
| Dec 18, 2021 at 14:12 | comment | added | Bimpelrekkie | Have you read: electronics.stackexchange.com/questions/309722/… ? As I mention there: it is not a proper memory cell. | |
| S Dec 18, 2021 at 14:09 | review | First questions | |||
| Dec 18, 2021 at 14:36 | |||||
| S Dec 18, 2021 at 14:09 | history | asked | It's probable | CC BY-SA 4.0 |