Timeline for using ram verilog instantiation
Current License: CC BY-SA 3.0
4 events
| when toggle format | what | by | license | comment | |
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| Oct 10, 2013 at 22:40 | answer | added | trayres | timeline score: 0 | |
| Oct 10, 2013 at 20:53 | answer | added | Greg | timeline score: 1 | |
| Oct 10, 2013 at 19:04 | comment | added | The Photon |
You probably need to set data to Z when you are not driving the bus. If this is meant for FPGA synthesis, you want to have separate data-in and data-out busses.
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| Oct 10, 2013 at 18:59 | history | asked | YAKOVM | CC BY-SA 3.0 |