Why are these voltage regulators seemingly using positive feedback?

Question

Looking over LDO / voltage regulator topologies I keep seeing examples of LDOs where the feedback network is connected to the non-inverting input terminal of the error amplifier.

Like this:

Taken from here.

Or like this:

Taken from here.

I found examples with the expected connection between the inverting input and output, but I am left to wonder how the circuits from above make sense.

Is this an example of positive feedback, an unknown to me circuit notation convention or something else?

Answer 1

You must consider the whole feedback, not just the error amplifier but also the transistor. It is the transistor that adds a 180° shift, which changes positive feedback into negative.

Answer 2

These two circuits look very similar, but the one on the left inverts, and the one on the right does not invert:

^{simulate this circuit – Schematic created using CircuitLab}

On the left is a "common source" setup, using a P-channel MOSFET, whose output (taken at the drain) is inverted with respect to the input at the gate. That is, as IN rises in potential, OUT1 falls, and vice versa.

On the right we have a common drain configuration, otherwise known as a "source-follower", employing a N-channel MOSFET. The word "follower" in the name suggests that the MOSFET's source (the output here) "follows" the input at the gate, implying that there's no inversion. In other words, a rise in potential at IN will result in a rise at OUT2. Conversely, if IN decreases, so does OUT2.

I explain this distinction in much greater detail in this answer.

The same difference in behaviour can be observed in bipolar transistor circuits, where inversion occurs in the "common emitter" arrangement, but not in "common collector" (also called "emitter follower"). The distinction is in where you derive the output signal. For the common emitter circuit, the output is the collector, and is inverted with respect to the signal input at the base, whereas the the emitter-follower does not invert:

^{simulate this circuit}

You'll notice that in all those circuits where you identified feedback returning to the non-inverting input, which seems to contradict how we usually implement negative feedback using the inverting input, feedback is derived from the drain of the transistor stage, which implies there's an inversion from that stage. They all use "common source" stages.

To obtain negative feedback, the goal is to have the op-amp output change in a manner that decreases the overall output, as that output rises. That is, the op-amp must oppose any change in overall output. If feedback were taken directly from the op-amp's own output, then that feedback must be applied to the op-amp's inverting input, so that a rise in output would result in the op-amp opposing that very rise, and vice versa.

However, in these circuits, due to the inverting action of the transistor stage, the overall output actually rises as the op-amp's output falls (and vice versa), and so to produce negative feedback that overall output must be coupled back to the op-amp's non-inverting input instead.

If there's an inverted relationship between op-amp output and overall output, which happens in all these examples due to the inverting transistor stage, then you must also reverse the op-amp's behaviour, by applying feedback to the non-inverting input instead. Otherwise feedback would be positive, in which a slight rise (or fall) of overall output would result in a further rise (or fall) in overall output, causing a much larger rise (or fall), and so on, running off to some extreme.

If you inserted another inverting stage (using an additional transistor or op-amp) between the existing op-amp and transistor stages, then you could once again apply feedback to the inverting input, as you would in classic amplifier designs. That's because the overall output, and the op-amp's output would once again be back "in phase".

If you replaced the common-source transistor stage with a common-drain stage instead, then again there would be no inverted relationship between op-amp and overall output, and you would also apply feedback (as usual) to the op-amp's inverting input.

Here are some stable systems successfully employing negative feedback. Note the number of inverting stages in the path between op-amp output and overall output, and see how an odd number of inversions requires feedback to be applied to the non-inverting input:

^{simulate this circuit}

In both circuits below we successfully employ negative feedback, but the difference between them is really subtle:

^{simulate this circuit}

Hopefully you noticed that the bottom transistor is configured as a source follower, which does not invert, and therefore feedback is applied to the inverting input, as usual. However, the top transistor is common source, that feedback signal is inverted with respect to the op-amp's own output, and overall output must be fed back to the non-inverting input for that feedback to be negative.

Answer 3

There's no positive feedback here. The output device is a PMOS, and thus, it is connected to the (+) input terminal to keep the loop negative.

To understand this better, on your left circuit (a).

1. Upward swing on \$V_{ref}\$ and constant voltage at (+) causes \$V_g\$ to go down (it's an small signal comparator).
2. \$V_g\$ going down causes Mp's drain (\$V_{out}\$) to go up. Signal inversion.
3. If \$V_{out}\$ goes down, so does \$V_{fb}\$, but by a factor of \$\frac{R2}{R2+R1}\$ lower in magnitude (i.e. equal to \$V_{ref}\$).
4. Thus, \$V_{fb}\$ has the same upward as \$V_{ref}\$. Therefore, V(+)-V(-)=0, thus we keep the error signal equal to 0, which is the whole point of a feedback system (In this case, for simplicity, assuming EA has infinite gain).

Follow the signal chain; there's no positive feedback.

EDIT:

About your question where to break the loop. It doesn't matter where you break it, because you are still in the loop. However, it matters what kind of source you use to excite the loop and compute the return.

And, actually, it's better not to break the loop, but instead insert a voltage or a current source such that the biasing is kept intact. This is useful for simulation, in particular.

In this loop (the amplifier on the left), we have 2 nodes where the right-hand impedance is high and the left-hand is low. Namely, \$V_{fb}\$ and \$V_g\$.

You can insert a series voltage with an AC amplitude of 1 (and DC = 0V) separating \$V_{fb}\$ from the (+) input of the op-amp. Then, in your simulator, you can simply plot \$\frac{V_{fb}}{V(+)}\$ (remember, you have to go around the loop, so you start from V+ and end in \$V_{fb}\$, which would your "output").

Likewise, you could also insert a voltage source in series with \$V_g\$, thus separating the op-amp output node and the PMOS gate. Thus, you can simply plot \$\frac{V_{o,EA}}{V_g}\$.

In any of those situations, the low-frequency loop gain would be equal to \$A_v g_{m,Mp} \frac{r_{o,Mp}R_2}{r_{o,Mp}+R_2+R_1}\$, assuming \$A_v\$ is the open-loop gain voltage of the op-amp, and the low-frequency signal model of the PMOS is just a \$g_{m,Mp}\$ with an output impedance \$r_{o,Mp}\$... and ignoring the load impedance.

If you'd do it at the drain of the PMOS, it'd be complicated because it's difficult to tell whether the impedance looking from at the drain of the PMOS is a lot higher than the feedback resistance, maybe it is. Same complication at the junction between \$R_1\$ and \$R_2\$.

To overcome this complication, Middlebrook came up with this method, where he uses the loop gain calculated from a voltage and a current source. He combines both results to produce a loop gain, and you don't have to care where you put these 2 sources. The only shortcoming of this method is that it doesn't account for reverse transmission, only for a forward transmission. But anyhow, it's still quite a good approximation to the true result for most electronic feedback systems.