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I tried to build a circuit as in picture below, where the LDO+MCU contains an Atmega328P, powered with an LDO:

enter image description here

In D3 cathode, there is a main rail supply, which can be up to 20V feeding the LDO and the MCU. The VUSB can be 5V, if present.

In theory: If voltage from J1 is between minimum operating voltage and 5V, I can choose from MCU to drive the PWR_CTRL. In this condition if PWR_CTRL is HIGH, the power is drained from the USB, otherwise from J1. If voltage from J1 is >5V, I always drain from J1, due to Kirchoff laws.

In reality, this is what happens (among other issued of minor relevance):

  • Bootstrapping the MCU with PWR_CTRL low, such pin is at middle voltage range when in reset. This bring to a lock condition which does not let the MCU to start (so far so good), but due to this intermediate condition, could happens that the MCU actually runs with such pin high, and so starts powered fully from the USB (no good), probably due to bad bootstrapping (the pin is set only once at startup). When system is locked without starting, so with intermediate voltage on T1 gate (so ok to me) -> a bit oscillation from the USB switching supply is amplified and reversed on T1 drain -> reversed again is present somehow amplified on Q3 drain -> almost completely cut off on D3 cathode (from 300mV to 30mV peak)
  • When the system bootstrap with PWR_CTRL high, when at J1 with voltage more than 5.6V the USB regulator starts oscillating up to 200mV at swithing frequency of the USB regulator attached to the usb port (it is a portable charger). This oscillation is only present in the VUSB net, and almost completely absent everywhere. This could sounds good, but in this condition, when the USB voltgae is present contemporary with 20V (or other lower values) on J1, the LDO absorbs a doubled current (from 12 to almost 24mA). This at 20V end with an LDO too much hot. So I supposed that some current flows from J1 -> LDO -> PWR_CTRL -> USB -> GND. Or USB -> LDO -> PWR_CTRL -> -> GND, but this last seems impossible, due to the diodes, and D3 is reversed with 15V applied on it.

What am I missing here?

PLEASE note that the goal of the question is not to find a solution that works, but to find why this solution have such issues.

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  • \$\begingroup\$ Can you define the requirements this circuit is intended to meet? \$\endgroup\$
    – ThreePhaseEel
    Commented Aug 7, 2016 at 15:40
  • \$\begingroup\$ I think that the only requirement is that it shall run with USB, power jack, and USB+power jack. Currents are very low, under 50mA, and the input voltage at power jack is at max 20V, min 3V (due to the LDO which outputs 3.3V). The USB is conceived to be conncted to a PC. \$\endgroup\$
    – thexeno
    Commented Aug 7, 2016 at 16:43
  • \$\begingroup\$ Which voltage do you want it to run from when both are provided? \$\endgroup\$
    – ThreePhaseEel
    Commented Aug 7, 2016 at 16:45
  • \$\begingroup\$ As explained (maybe not so well) when the J1 is <= of 5V, with the USB present, I can choose by driving the MCU pin. If J1 is greater than 5V, it can only run from J1 since it is greater than USB. \$\endgroup\$
    – thexeno
    Commented Aug 7, 2016 at 17:00
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    \$\begingroup\$ Clean up the schematic and export it from Eagle properly. The vertical text is annoying to look at, and all those origin crosses simply don't belong there. A draftsman wouldn't give you a drawing with construction lines still in place either. Dumping slop on the volunteers here you seek a favor from is not a good idea. \$\endgroup\$
    – Olin Lathrop
    Commented Dec 6, 2016 at 11:48

2 Answers 2

Reset to default
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Instead of cobbling together discrete parts and hoping to get the result you are after, this is more simply and foolishness-resistantly done with a dedicated IC: Linear Tech's LTC4412. The circuit below should get you started.

schematic

simulate this circuit – Schematic created using CircuitLab

Note that PWR_CTRL in this circuit is HIGH to select Vbus and LOW to select Vusb when both supplies are connected.

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  • \$\begingroup\$ Ok, thanks, that is nice, uses a P-MOS like mine, but the component has some cost. Anyway, I asked this because I like to know why my solution does not work well. \$\endgroup\$
    – thexeno
    Commented Aug 8, 2016 at 9:12
  • \$\begingroup\$ LT(C)XXXX = expensive. \$\endgroup\$
    – winny
    Commented Dec 6, 2016 at 12:48
  • \$\begingroup\$ @winny -- I don't disagree that the Linear parts aren't el-cheapo, but you get what you pay for ;) \$\endgroup\$
    – ThreePhaseEel
    Commented Dec 6, 2016 at 12:48
  • \$\begingroup\$ Yes, well at some point they need to make the money back from supplying LTspice for free. :-) \$\endgroup\$
    – winny
    Commented Dec 6, 2016 at 13:00
  • \$\begingroup\$ I'm done with TI, I've had too many undocumented features in their parts and no way to get a hold of them. You do get what you pay for. \$\endgroup\$
    – Voltage Spike ♦
    Commented May 18, 2018 at 19:39
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What am I missing here?

  1. Q3 is a P-channel FET and is upside down in the circuit. Examine its body diode in the symbol.

  2. D1 may be stressing your MCU output if it is not configured as Open Collector.

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