There are several errors in this circuit, some are pretty gross. First, the single-supply voltage requires the op-amps to work voltage levels a little bit higher than zeroV, not most op-amps can do it, 358 and 324 will not!
Then, R15 should produce something higher than 50mV per Ampere, or the op-amp will not answer by working pretty close to rail. Suppose R15 is 1Ω, then 1A will deliver 1V on the non-inverting input of U2, its output will raise until the inverting input would be also 1V. For that to happen, the resistors R12+R13 and R14 form a voltage divider, what makes U2 to amplify by the factor 1+((R12+R13)/R14).
Lets see, suppose R13 is set to zero, so U2 gain will be 1+(100k/1k), or, 101. Then, to have 1V on the inverting input, U2 output should be 101V, what is ridiculous, will never happens for two reasons, first, VCC is only 15V, and second, U2 would never support such high voltage. So, that statement 1V/A at the output is completely wrong. For that statement to be true, R15 should be 0.01Ω, not 1Ω.
But then, you go into another problem. Most old op-amps can not work very well with voltages close to a rail, in this case, single supply, it limit low voltages on the input and output. With 0.01Ω at R15, it means 10mV at U2 non-inverting input, it will not work well, some op-amps have more than that just as offset error between the inputs.
I would recommend to use 0.1Ω, 0.5Ω or even 1Ω at R15 for those reasons. If using 0.5Ω, the U2 gain could be set to 2 in order to have 1V/A at the output. So, R11 and R14 could be 10k, R12=8k2 and R13=5k (4k7) potentiometer, in order to have a fine adjustment of U2 gain, with R13 centered for U2 gain of 2, having 1V/A at output.
Then comes the circuit of Q1. It seems the designer had a full bag of 50kΩ potentiometers, since he used them all over without any calculation. Pot R1 is totally unnecessary, since you can control the voltage at the emitter of Q1 by R5 adjustment. Also, serving as a emitter follower bias base resistor, R1 should have a lower value, a maximum of 10k will be in order. R6 makes no sense in series with the base, it is a protection for the base if R5 cursor touches the 15V on the supply, so, R6 should be between R5 and VCC.
Also, a 12V (15V) zener diode must be inserted between gate and source of the mosfet, when you power on the circuit, if DUT is higher than 20V, a pulse of current through the internal capacitor Drain to Gate (CDG) will deliver a voltage on gate that could be higher than the gate could support, damaging the mosfet.
Also, the left side of R4 could be connected directly to the top of R15 (mosfet source), making both things independent; the display of V/A of U2 and the feedback control of the mosfet via U1, so, in case of any problem (short circuit or low impedance) at the monitor, will not interfere with the current regulation. I am pretty sure that this circuit as shown was never tested, it will not work.