You say that both boards A and B get a common data signal from which they are both able to generate the output SYNC signal. You have to think carefully about the process of how the boards derive the sync signal from the data signal. If that derivation process is in any way done with the local oscillator on the board as a base reference then you will have jitter between the SYNCs from the two boards.
The reason for the jitter is that the the oscillator on one board will have at a minimum one clock cycle of uncertainty (could be many more) of how the sampling of the data signal is done to how the SYNC can be generated. In addition the two oscillators will most certainly be out of phase and slightly different frequency. This adds to the sampling jitter as mentioned in the previous sentence.
If the data signal decoding and SYNC signal generation was not at all dependent on the oscillator then there is much greater chance that the two SYNCs would be more in line with each other. But there is highly likely for there to still be jitter due to the variations of circuit delays and voltage thresholds in the two separate boards. Even things like variation in the power supply voltage in one board can shift circuit delays and thresholds.
Most systems are much more complex than looking at just the effect of a single oscillator clock. If the "data signal" is fed into an MCU and software is involved in the detection of the data and the subsequent generation of the SYNC signal then the jitter may be even more pronounced due to factors related to code fetch caching, software loop times and interrupt latencies.
If it is required that the SYNC outputs be in very close synchronization there needs to very careful evaluation of the design techniques used. If the oscillators have to be a fundamental part of the system at each board then it is normal to need to use a PLL technology the lock the oscillator to frequency characteristic of the input data signal. This can remove the uncertainty due to differences in oscillator phase and frequency provided the data signal has sufficient preamble built into it to cover the PLL sync and lock times.
In addition you would try to find ways to eliminate gross jitter caused by using software to decode and generate signals. Instead use as simple of analog and digital circuits that are purpose designed to assure deterministic behavior in the data decoding and sync generation process.
This is all a high level overview of the problem. There are many complex and detailed techniques that engineers have devised over the years to eliminate or work around jitter (i.e. non deterministic behavior). It is even possible to have MCU software involved in such algorithms with very careful design. But with that said these days it would be more typical to see FPGAs used for such designs where ample parallel logic can be deployed to perform the digital task and many such parts contain sophisticated DPLLs that can provide good clocking synchronization.
