ICSP + SST25VF016B + ATmega2560 Problem

Question

We have designed a board that uses an ATMega2560 and wanted to have the option to do remote firmware updates (it has a Sim800C as well for getting the firmware files).

Therefore we've added an SST25VF016B memory module (to store the firmware) and coupled it with a Logic Level Converter (as Atmega is operating on 5V and the SST25VF016B at 3.3V).

Our schematic is the following:

The problem we are facing is that we cannot program the ATMega when the SST25VF016B is soldered on our board. After searching for a bit, I've found this Note from Atmel:

Shared Use of SPI Programming Lines If additional devices are connected to the ISP lines, the programmer must be protected from any device that may try to drive the lines, other than the AVR. This is important with the SPI bus, as it is similar to the ISP interface. Applying series resistors on the SPI lines, as depicted in Connecting the SPI Lines to the ISP Interface, is the easiest way to achieve this. Typically, the resistor value R can be of 330Ω. This enables to program all the devices through a minimal interface. However, if there are no special design considerations, then all the AVR devices will respond to the ISP instructions. The SPI clock lines should be separately provided (can be gated using jumpers or DIP switches) so that only one of the AVR devices receives SPI clock at a time. Other SPI lines (MOSI and MISO) can be shared. This method ensures that AVRs are separated from the programmer by the same protection resistors, since they are all held in RESET while the ISP reset line is activated. The ISP clock can be gated using jumpers or DIP switches. An alternate solution is to use multiple ISP interfaces, one for each device, all protected separately with series resistors.

Question is if anyone has done something similar and knows that it will work. Also, how could I use multiple ISP interfaces one for each device that is mentioned at the end ?

Answer 1

The bomb-proof method of doing this is as below

When programming via SPI (I'm assuming you're using AVR-ISP or the latest version of it to do the initial production programming), the unit is held in reset. So, this method isolates all SPI from the processor other than the programming unit.

Be careful with the reset chip, I've been caught out by a push-pull output that takes control of the reset line and have got over that with an open drain device or a series resistor between output of reset chip and rest of the circuit.

You can use a 4053, doesn't have to be a 74HC.

Answer 2

The conflict arises from the permanent enable of the single driver for MISO which is facing towards the ATmega - you need to make that enable contextual on flash vs. ISP operation.

If the timing of your usual SPI cycle has the flash chip select low for the entire time that you are expecting a reply from the flash, then all you really need to do is:

1) Drive the /G4 enable from the ATmega's side chip select, ie PCO_53

2) Make sure that this and the chip select will be high during programming operations - for example, add a pullup resistor.

(It's typical to keep /CS low for the entire cycle, but a few parts allow you to take it high early and still complete the transfer, but this is rarely required so you can just make sure to keep it low until the end).

You should be able to try this with a fairly minor rework to your existing board - bend up pin 13 or cut the trace, jumper it to pin 9, fit a resistor somewhere.