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I'm trying to drive a 5V 200mA fan from a PCF8574 powered by 3.3 V. For context, I asked a separate question about using active low vs high on this expander, and @Justme recommended using a high-side PNP (instead of a low-side NPN with a PNP driver), driven low by the GPIO.

You could use a single 200 mA PNP transistor or P-FET as a high-side switch from the GPIO to drive the fan.

Note: JM said single PNP, inferring to me that the base would be connected to the GPIO, unless perhaps this wasn't considering the voltage difference?

A single PNP would be desirable as I'd like to reduce the number of BJTs in my circuit.

However, I read in an answer to a question about PNP high-side switching that you shouldn't connect the base of the PNP to a device which has a lower voltage, as you'll fry the device.

There is a temptation to think that we could do the same trick with an PNP transistor as shown in Figure 1b. The problem is that the emitter-base junction is always forward biased. This will apply the 12 V to the chip output and destroy it or, if there are protection diodes on the output, the current will flow through the protection diodes into the micro-controller supply (shown as 5 V in this case). The effect of this current flow is to turn on Q3 and the load can not be switched off.

So, should you insert an NPN between the PNP to protect the GPIO, as you would on a micro? I'm scratching my head here wondering if I'm missing something or if I'm misinterpreting JM's tip.

PCF8574 with high side PNP

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  • \$\begingroup\$ Note that some 3.3 V devices may have pins which are 5 V tolerant, so the single-PNP could work with those devices. Yet, such devices could also have a power-application requirement (3V must come up before 5V.) \$\endgroup\$
    – rdtsc
    Commented Nov 4, 2022 at 18:55
  • \$\begingroup\$ If it is ever possible for 3.3 to be absent when 5 V is present, then you MUST use two transistors, otherwise the PCF8547's de-energized output will sink current and turn on the PMOS or PNP transistor. NOTE: I don't know what a PCF8547 is, but the vast majority of all electronic devices will sink current through their outputs when the IO voltage is not present. \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 7:43
  • \$\begingroup\$ I would for sure use PMOS not PNP. Not sure why you are favoring PNP in this case. \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 7:44
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    \$\begingroup\$ I strongly suggest that you use two transistors (preferably one NMOS and one PMOS). You can use BSS138 for the NMOS. For the PMOS, you want one with a low Rds(on) rating specified at Vgs = -4.5 V. In your case with a 200 mA load, I think you want Rds(on) to be 100 mOhms or something less. There should be lots of options. These transistors are pretty small. \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 7:50
  • \$\begingroup\$ Another option is to power the PCF8574 with 5 V and use a level shifter on the I2C signals so that you can control the bus expander from a 3.3 V I2C source. Then you could use a single PMOS high side switch. \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 18:06

6 Answers 6

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Yes, definitely insert the NPN transistor. Otherwise if you try to use the 3.3V GPIO the PNP base will leak into the GPIO and never turn off.

(Note: your diagram shows the GPIO being powered by 5V. I assume you meant for that to be 3.3V.)

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  • \$\begingroup\$ Thanks for clarifying. Is there a way to use a single transistor in this scenario? Or is it always going to require either two on the high side or low side? Maybe there's a way to use a P-FET? Though how would I saturate the gate with only 3V3? \$\endgroup\$
    – Nick Bolton
    Commented Nov 4, 2022 at 18:30
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    \$\begingroup\$ You not only have to prevent the leak path, but also guarantee that the base is biased fully off, which means above 4.3V (5V-Vbe). So you don’t have a choice, you need the NPN level shifter if you want to switch high-side. Low-side could use just the NPN. \$\endgroup\$
    – hacktastical
    Commented Nov 4, 2022 at 18:34
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    \$\begingroup\$ You don’t really need to saturate the base of the NPN because it’s driving another another base. But you can use a FET, like a 2N7002 or BSS138, instead of the NPN. \$\endgroup\$
    – hacktastical
    Commented Nov 4, 2022 at 18:42
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    \$\begingroup\$ Yes. Both those FET types have Vgs thresholds of about 1.5V \$\endgroup\$
    – hacktastical
    Commented Nov 4, 2022 at 19:08
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    \$\begingroup\$ It depends on the requirements of your load. If the load doesn’t have to connect any other signals then low side can work (like a two wire fan for example). Otherwise, high side is preferable. \$\endgroup\$
    – hacktastical
    Commented Nov 4, 2022 at 19:25
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If you can tristate the pin and it is 5v-tolerant*, it will work with just the PNP and a base resistor:

  • pin low turns the PNP on
  • pin high turns the PNP on
  • pin tristate turns it off

* as noted by mkeith, your bus expander is not 5V tolerant, so this will not work in this specific case.

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  • \$\begingroup\$ The datasheet for the bus expander says that the output pins should be kept below VCC + 0.3 V. So if VCC is 3.3 V as the OP shows, then the pin is NOT 5 V tolerant. If VCC can be increased to 5 V, then all is well. But in that case, the inputs must be level shifted to 5 V too to insure correct logic levels. \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 8:25
  • \$\begingroup\$ > "your bus expander is not 5V tolerant" -- thanks for highlighting this. Unfortunately, I learned this the hard way (before asking my question) and fried a couple of expanders. \$\endgroup\$
    – Nick Bolton
    Commented Nov 5, 2022 at 11:27
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Not a product recommendation, but in my case there are multiple loads to drive from the GPIO and the aim is to reduce the BOM, so I'm considering that using a Darlington array IC might be one approach.

Darlington array

Block diagrams

Gotcha: Watch out for the ULN2002; it has a 7V Zenner at the base of each Darlington, as it's "designed specifically for use with 14-V to 25-V PMOS devices" on the input. In other words, it won't work with low voltage (i.e. 3V3 or 5V) TTL at the inputs. I mistakenly ordered this part without realising, so to use this part in my circuit I'd have to use PMOS to drive the inputs, which in my case partly defeats the aim of BOM reduction.

ULN2002

(Image source: Texas Instruments ULN200x datasheet)

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  • \$\begingroup\$ I'm considering that using a Darlington array IC might be one approach. .. Gotcha: Watch out for the ULN2002: "(Jay:) No, Holden McNeil--what's important here is that " you seem to be having a lot of fun in this series of three posts, electronics.stackexchange.com/questions/641165/…, electronics.stackexchange.com/questions/641283/…, and this.ref. Congrats! \$\endgroup\$
    – V.V.T
    Commented Nov 6, 2022 at 4:48
  • \$\begingroup\$ How deep can I dig? \$\endgroup\$
    – Nick Bolton
    Commented Nov 6, 2022 at 7:27
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    \$\begingroup\$ dunno. Call 811 \$\endgroup\$
    – V.V.T
    Commented Nov 6, 2022 at 9:16
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Do the same as with the expander driving a LED from 5V. Same thing really.

I believe you wanted active low because IO expander defaults to high (under the specified conditions).

If there is 2V drop from Veb and something else to expander pin, it will work. High will be off and low will be on.

You can add a LED, or a few diodes. Transistor is a good idea too.

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This is how I would do it. PMOS M2 should be chosen to have minimal voltage drop at your load current. I think your load current is 0.2 amps, right? So maybe we should specify that Rds(on) for M2 should be 100 mOhm or less. Often, power MOSFETs list Rds(on) at different gate voltages. We want to see Rds(on) of less than 100 mOhm at Vgs 4.5 volts. Sometimes for PMOS the datasheets say -4.5 Volts to kind of emphasize that it is PMOS and that the gate should be BELOW the source to turn it on.

The diode D1 is probably not needed. If the load is inductive or if there are long wires between M2 and the load, then D1 may be a good idea. It is to prevent voltage spikes when M2 is turned off. But most likely M2 will turn off so slowly that there will be no inductive spike in the first place.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ What's the advantage of using a high side PMOS instead of a low side NMOS in this case? Or, would either approach work fine? Does a high side PMOS introduce less resistance? \$\endgroup\$
    – Nick Bolton
    Commented Nov 5, 2022 at 11:48
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    \$\begingroup\$ Low side can work, however, I have had enough problems with low-side switches over the years that I usually just go straight to the high-side whenever possible. The problem with low-side switches is that it is very easy to overlook some type of sneaky ground connection that bypasses your switch and causes your load to turn on or at least leak when you weren't expecting it. If you do a low side switch you can probably get away with just using one NMOS (but not the BSS138... it is not a good fit for a 200 mA load). \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 16:55
  • \$\begingroup\$ Hmm, yes, sneaky ground shorts. Hence specialised high side load switch ICs. \$\endgroup\$
    – Nick Bolton
    Commented Nov 5, 2022 at 22:26
  • \$\begingroup\$ You can use the ICs too. I always just use PMOS. \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 23:11
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It should be possible to switch a 5 V load using 3.3 V logic and a PMOS device with a gate threshold such that it is fully ON at 5 V and OFF at 5-3.3 = 1.7 V. I chose a MOSFET with Vto = 2.4 V. I added a voltage divider so that the output pin would never see more than 3.3 V, but that is optional.

PMOS Switch 3.3V to 5V

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  • \$\begingroup\$ possible yes, but given the large variation in FET threshold voltage, would require hand selection. \$\endgroup\$
    – tobalt
    Commented Nov 5, 2022 at 7:08
  • 1
    \$\begingroup\$ This is playing with fire. You need something that is guaranteed to be on when Vgs = -3.3 V and guaranteed to be off when Vgs = -1.7 V, and then when you add in the other variations (like min and max for the 5.0 and 3.3 V rails including normal temperature variation) and it is very unlikely to work well. \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 7:46
  • \$\begingroup\$ Actually I guess I stated it wrong. Guaranteed to be on when Vgs = -5 V. So not that requirement is easy to satisfy. I am more worried about finding something that is guaranteed to be off when Vgs = -1.7 V. All these little SOT-23 PMOS switches for high-side bus switching have very low gate threshold voltages, some as low as -0.8 V. \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 8:07
  • \$\begingroup\$ I don't think the margins are that close. When the input is low, the gate voltage is -5V, which will turn on any logic level rated MOSFET. And when the output is high, the gate voltage is -1.7V, so a device with a threshold of -2V to -3V should work just fine. Once you choose a suitable device, the threshold should not vary all that much. \$\endgroup\$
    – PStechPaul
    Commented Nov 5, 2022 at 8:10
  • 1
    \$\begingroup\$ Vgs(th) min for the Si7465DP is 1 V at 25 C. \$\endgroup\$
    – user57037
    Commented Nov 5, 2022 at 8:34

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