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Consider:

enter image description here

Attached schematic is from a broken sampling scope that I have in the lab. Cathode of D1 is connected to a sampling gate output, which is sealed in a metal cage.

U5 (top right) is the signal amplification chain, and the rest of the signal chain can be found in this link: here

From this figure, the part that I am not 100% convinced is the signal interaction between U9.OP1 output and 100 MΩ resistor (highlighted in blue).

I guess the purpose of U9 is to set the gate of Q5.2 to be close to the gate voltage of Q5.1, but from DC perspective there is 100 Mohm resistor placed b/w Q5.2 and U9.OP1.

Meanwhile, the sampled signal from the sampling gate is connected to D1. This needs to be tossed to U5 for filtering and amplification, but I worry about the output impedance of U9.OP1 - if this is working as an ideal opamp, isn't the output impedance supposed to be very low? if so, then the signal from D1 will experience significant attenuation, right?

I would really appreciate if anyone can explain the feedback mechanism shown in this diagram!

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  • \$\begingroup\$ The schematic could use redrawing for better clarity. But it's not complex. U9 is wired correctly to force the JFET gate voltages to be identical. Even the smallest difference between them is countered. And the JFETs will be reverse-biased, so only tiny leakage currents (picoamps, likely) are involved at their gates. You've got very stiff biasing of the PNPs so that about 15 mA is generated through the 510 ohm resistors, About 5 mA of that is siphoned off by the JFETs, leaving 10 mA for the PNP collectors. The opamp senses any current differences and adjusts to re-balance them. \$\endgroup\$ Commented Aug 6, 2023 at 9:11
  • \$\begingroup\$ I understand the circuit behavior, in isolation. But I didn't know what to write as an answer. I've given a synopsis of what I see. Just no details. I can provide those. But I've no idea if that matters to you. (Can't tell from reading. Could just be me.) \$\endgroup\$ Commented Aug 7, 2023 at 3:52
  • \$\begingroup\$ @periblepsis I also read through circuit concepts from old Tektronix books, and I believe this is some sort of a memory circuit that is driven by a memory gate. From my understanding, the isolation is there so that it only allows signal to pass through when a sampled signal (in a pulse form) hits the cathode of diode. This way, it stores the received pulse over the capacitor, and the rest of signal chain will filter and amplify it. In short, I believe the circuit doesn't do anything in DC (b/c of isolation). the input signal must be mixed with a strobe signal \$\endgroup\$
    – Emm386
    Commented Aug 7, 2023 at 4:14
  • \$\begingroup\$ @periblepsis but I also would like to hear your opinion! \$\endgroup\$
    – Emm386
    Commented Aug 7, 2023 at 4:16
  • \$\begingroup\$ I can only describe what I see. Not what I cannot see. And I see nothing attached to D1 or to VG1. Both of those facts make me unable to provide/have the context for understanding the circuit's role. I can discuss what it does. But not why. As before. Because, while I understand what a sampling scope does, I have never designed one. I've seen block diagrams that make sense to me. That's it. But knowing something from having completed one is quite different from knowing something from a highly simplified block diagram. Reality impinges. So I'm very uncomfortable for that reason. \$\endgroup\$ Commented Aug 7, 2023 at 4:21

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Here it is. I'm just providing rough numbers. I did not run this through LTspice or attempt any precision in modeling.

So when I show that the emitters are at \$5.4\:\text{V}\$ then I compute the current through \$R_3\$ and \$R_4\$ as \$\frac{13\:\text{V}-5.4\:\text{V}}{510\:\Omega}=14.9\:\text{mA}\$. But I round it as the base-emitter voltage will vary with part and temperature, if not other reasons.

Same thing with the current sink formed by \$Q_3\$. I got rid of that and just approximated it as a simple current sink.

schematic

simulate this circuit – Schematic created using CircuitLab

\$U_9\$ is arranged so that if the gate of \$Q_{5.2}\$ were to drop slightly, then its drain current would also drop slightly. This would mean more current would pass through \$Q_{5.2}\$. That would cause the drop across \$R_6\$ to increase, which would increase the voltage at the (+) terminal of the opamp, which would drive it's output upward, which would pull back up on the gate of \$Q_{5.2}\$, correcting the situation. This is NFB, of course.

JFETs are operated with reverse bias and their leakage currents are in the low picoamps. (I'm concerned about leakage in \$D_1\$, though.) So the \$100\:\text{M}\Omega\$ resistor will barely have any voltage drop across it. Hence, the opamp output will be quite close to both gate voltages. A signal placed at VG1 will be reflected at the output of the opamp. In every sense, the two JFETs float above the current sink, their gates tracking each other and VG1.

\$Q_{5.1}\$ is self-biased, without any input on VG1, and the opamp will track that. But I don't know what's tied to VG1. Also, \$R_7\$ and \$C_1\$ form a simple RC filter for VG1, obviously. So \$Q_{5.1}\$'s gate sees a low-pass filtered result from VG1.

The other kink here is \$D_1\$. So long as \$D_1\$ is reverse-biased (not much, though, as again I remained concerned about reverse bias leakage via \$D_1\$ as it affects things via \$R_8\$), the above description holds and the voltage gain vs VG1 is 1 (excepting that \$C_2\$ can be a bit "peaky" if the value is at low parasitic levels.) Above about \$47\:\text{pF}\$ it's probably fairly flat but then \$C_2\$ may be setting the upper bandwidth limit.

But if \$D_1\$ becomes forward-biased, then \$Q_{5.2}\$'s gate will track that input and ignore the opamp output. Since \$D_1\$ can only conduct in one direction, \$Q_{5.2}\$'s gate can only be pulled down, not up, meaning that less current will be diverted there and more via \$Q_{5.1}\$. There will be a narrow range over which GATE can operate to yield extremely high gains nearing as much as 200, or more. But we are talking about a few hundred millivolts around whatever is at VG1, at most, because that's how this differential pair will work.

So how GATE is driven/used/whatever is really important. If it is pulled enough negative relative to VG1, then VG1 will be ignored. It it is pulled enough positive (so as to reverse bias \$D_1\$ -- and there my concerns over leakage pop up again) then the opamp output tracks VG1 with a gain of about 1 (depending on the values of the capacitors, of course.) Here, though, if GATE is driven by a low impedance source then leakage through \$D_1\$, amplified greatly by \$R_8\$, may be a problem.

If it is in the sweet spot, say a hundred millivolts above or below VG1 to just pick something, then GATE sets the gain applied to VG1. (That sweet spot, so to speak, occurs because \$D_1\$ is only diverting a little current and that allows the gate of \$Q_{5.1}\$ to be amplified a lot by the opamp. And a problem with that idea is that \$D_1\$ may still have some leakage amplified by \$R_8\$.)

If GATE is well below VG1, then the opamp will probably just rail at its positive supply and ignore VG1. I'm not sure if that's desired. (Probably not.)

The leakage in \$D_1\$ and that value of \$R_8\$ would suggest that GATE should closely follow VG1 (within 10's of millivolts) for the opamp output to accurately track VG1 and that GATE should be set well below the most negative excursion of VG1 to cause it to be ignored, with the opamp railed/saturated.

That's my limited perspective on it. I've no idea how VG1 or GATE are being used. So guesswork only. Best I can do, ignorant as I am about the details of designing a complete, successful sampling scope.

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  • \$\begingroup\$ thanks a lot for leaving a detailed explanation, as always :D. I 100% agree with all the analysis you did. On top of this analysis, I'm also very convinced that this amplifier works as a lossy integrator with input coming from cathode of diode as a pulse. This pulse will be integrated and toss to U5 at the end. I think they chose integrator to make sure SNR penalty is minimized, and for the sampling scope purpose they only care about final integrated value. \$\endgroup\$
    – Emm386
    Commented Aug 7, 2023 at 18:57
  • \$\begingroup\$ In fact, I have one extra question regarding this topology: why do they need to use Q5 & Q7? why can't they just use U9 directly? My rough guess is... they may need to get some extra loop gain on top of gain of U9. But I also would like to hear your opinion on this. \$\endgroup\$
    – Emm386
    Commented Aug 7, 2023 at 19:20
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    \$\begingroup\$ @Emm386 You mean, why not just put the opamp across the drains of the two JFETs and control the gate of one of them with the opamp, rather than go to this extra trouble? I have an idea, having to do with how VG1 and GATE are supplied. But there's no information about any of that, so I can't confirm or refute that thought. If there is an independent reason, one that doesn't require knowing anything about VG1 or GATE, then perhaps this is a good question to ask separately and to be answered by experts and not an untrained hobbyist. \$\endgroup\$ Commented Aug 7, 2023 at 23:09
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    \$\begingroup\$ thanks a lot for your thoughtful comments! as always, I learn a lot from your responses! \$\endgroup\$
    – Emm386
    Commented Aug 7, 2023 at 23:52

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