Reducing the fall-time of a P-channel MOSFET

Question

I have implemented the following circuit in hardware.

My required output across load (R7) is a pulsed signal of 20 V, 100 kHz, 10% duty cycle (10 us pulse width and ON-time of 1us and OFF-time of 9 us).

My load would be varying from 2-10 Ω. For each value of the load, I require a minimum of 10 A.

Results for various frequencies:

500 mHz:

800 mHz:

2 kHz:

5 kHz:

9 kHz:

10 kHz:

11 kHz:

From the pictures we can observe that the ON-time of the MOSFET is decreasing as the frequency is increasing. Thus, the signal shape obtained is in the form of a sawtooth and not a perfect pulse. There are also some overshoots in the signal. Also, upto 10 kHz, the low level of my output signal is reaches 0 V. From 11 kHz onwards, the low level of the output signal does not reach 0 V. As a result, the output voltage is decreasing as we are increasing the frequency.

Please suggest the required changes to solve the above issues in the circuitry to decrease the fall time and get a perfect pulse upto 100 kHz with 10% duty cycle and also to remove those overshoots.

I want to increase the battery voltage to 30 VDC, to obtain a 30 V pulse at the output. In this case, if I'm using a potential divider circuit to restrict Vgs to be below its maximum rating of 20 V, the charging time of Cgs is increasing which is resulting in increased rise time of the MOSFET. Is there any better approach to this?

The part number of the MOSFET is SQM120P10_10M1LGE3 mosfet datasheet

Answer 1

Here is a modified circuit:

I didn't use the exact MOSFET model. The one you are using has a lot of gate charge. Also note the absolute maximum Vgs is 20V, but that's typical of such parts.

Here is the same circuit but with an AOD4185 (dissipates about 1W typically):

If you want to keep the BJT, add a Baker clamp:

Answer 2

Q10 base current is four times collector current. That is wrong. Q10 is oversaturated. Ib should be 10 times less then Ic.

You don’t need R14 and R15 since they drive followers.

Remove R18 and place it to gate.

Answer 3

There is substantial voltage overshoot, which means there's a problem either with supply decoupling, probing technique, or both:

If you want fast switching time, it's not going to work on a breadboard because the inductance of pretty much everything is too high. You need either a well laid out PCB, or a bit of blank copperclad PCB to act as a ground plane, and sticky copper tape.

It's always a good idea to add a gate resistor, even low value, to prevent oscillations as the MOSFET switches.

In any case you need substantial decoupling on the power supply to lower its impedance, but how much?

You want a 10µs 10A pulse with a flat top (presumably) so the on-board power rail should have low impedance in the 100kHz-1MHz range. If you use a switching power supply with big output caps and short wires you may get away with just a bunch of MLCCs in parallel on your board.

If you're using a bench power supply it's a different story: these usually have quite low capacitance on the output in order to be able to apply the current limit quickly. In addition they tend to have a bit of a slow reaction time when switching from low load to high load, as your circuit does. So in this case you will need a low-ESR electrolytic on your board.

Since you mention 10A into a 10 ohm load this implies a 100V power supply, in this case large capacitance MLCCs will be expensive. A better compromise would be smaller MLCCs with several low-ESR electrolytic caps in parallel. Several physically smaller caps in parallel will have much lower inductance than one large cap.

It's important to check the caps do not create a resonant LC circuit with the wiring inductance and the power supply.

Once this is done, next problem is your MOSFET: its gate charge is enormous for its RdsON.

If you intend to go to 100V you can't use a 100V MOSFET, you need some safety margin, so at least a 150-200V MOSFET. Problem is, high voltage PMOS are not that good and hard to find compared to NMOS.

I don't think you need 10mOhms RdsON. Even with 10A current, a 10mOhm MOSFET will dissipate 1W when ON continuously, but with your 10% duty cycle pulses you can certainly get away with 100mOhm RdsON.

Unless you put a ton of caps, you're not going to get 10mOhm power supply impedance anyway, so you'll have some voltage drop.

In order to drive the MOSFET, the simplest solution is to use a gate driver chip, but this one is more intended for NMOS. So it will apply its full supply voltage on the PMOS gate. Your circuit does the same: with more than 20V supply, the MOSFET's maximum Vgs will be exceeded and it will be destroyed.

So you'd either have to find a chip that will limit the voltage or power it from a 12V supply hanging from the main supply and level shift the input. It's cumbersome.

Another solution is to use a NMOS, there are plenty which fit your needs. The NMOS will have lower gate charge and/or RdsON and switch faster. Then a bootstrap driver like this one which creates a supply higher than the supply rail by using a bootstrap cap. This means it will only work if the load pulls the output to ground to recharge the cap when it is switched off. Since you intend to make pulses, it's not a problem.

Answer 4

In the circuits below, C1 represents gate capacitance, the chief reason you can't have nice vertical edges, and why you need Q8 and Q9 in the first place:

^{simulate this circuit – Schematic created using CircuitLab}

Most importantly, I've included power supply decoupling, with C2 and C3, which are conspicuously and sinfully absent from your design. These are critical reservoirs of energy available to accomodate ridiculously fast-changing current demands. Demands that cannot be met by the power supply alone, due to inductance in the various current paths here. C2 should be ceramic. These capacitors must be connected as close as possible to the load ground, the MOSFET's source, and the collectors of Q8 and Q9. All current loops in that region need to be as tight as possible to keep inductance to a minimum. C2 and C3 might seem unimportant, but they can and will make a huge difference in performance.

In the first design I've merged the 10Ω collector resistances R19 and R18 into a single resistance R20 at the emitters. I don't know why you placed them in the collector paths, but it doesn't make sense since Q8 and Q9 are emitter followers.

R11 and R14 are not necessary, again because of the emitter followers, so they're gone. In any case they only throttled much needed base current.

In the circuit underneath I am preventing Q10 from saturating with R21, which also makes R10 redundant. This will dramatically improve Q10's switch-off speed. It also prevents Q10's collector potential (and consequently gate potential) from falling all the way to 0V, alleviating the need for additional clamping to constrain gate potential.

I've also reduced R11, since you need as much base current for Q8 and Q9 as possible.

Here are plots of input and gate potential:

You still have a problem though, take a look at the graphs of gate current:

Those peaks of over 1A in either direction exceed the absolute maximum peak collector current for Q8 and Q9. For the 2N5551, that's only 600mA. While it may work for now, I don't think Q8 and Q9 would last very long. You could mitigate this by using a larger R20, but the price you pay is slower gate transitions.

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I forgot to mention the overshoots. These come from gate-to-drain coupling of the extremely rapid rising and falling of gate potential, due to the capacitance between gate and drain.

That capacitance is a real b*tch, and causes many headaches. The coupling goes the other way too; sharp potential transitions at the drain (across the load) get coupled right back to the gate, opposing whatever you're trying to do at the gate. You try to switch off the MOSFET by raising gate potential, but drain goes shooting downwards, tending to lower gate potential instead. The MOSFET can even switch itself back on, momentarily. This is called the miller effect, and is a compelling argument for proper, strong, gate drivers.

Anyway, the solution to these overshoots and miller effects is not trivial. It could be as simple as an RC snubber across the load, or it might require a much better, lower impedance gate driver. Or perhaps there's nothing you can do about it, and you just have to accept that overshoots and ringing are inevitable to some degree. A lot depends on the load itself, and it's a big topic, a big headache.

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Lastly, your choice of MOSFET is not great. It's \$V_{GS(TH)}\$ could be as low as 1.5V, and typically these so called "logic level" devices have very high input capacitance. That capacitance will obviously hamper fast transitions.

Since you are able to obtain \$V_{GS}\$ up to the full 20V acceptable for most MOSFETs, you can afford to use a device which is much less sensitive to gate potential, perhaps having \$V_{GS(TH)}=5V\$ or even more. This will often be accompanied by a much lower input capacitance.

Your use of emitter follower Q9 prohibits gate potential from rising above \$V_{SUPPLY}-V_{BE}=30V-0.7V=29.3V\$. In other words, \$V_{GS} \ge 0.7V\$, always. As a result, the MOSFET will always be precariously close to \$V_{GS}=1.5V\$, where it will begin to switch on.

Looking at the voltage graphs above, it's clear that the rising gate potential crosses this 28.5V threshold very late in the curve. By using a MOSFET with, say, \$V_{GS(TH)}=5V\$, the threshold changes to \$30V - 5V = 25V\$, a point which is crossed much earlier. The slope of the graph there is also much steeper, faster changing, meaning that the MOSFET will spend less time in transition from on to off.