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I have a rechargeable coin-cell that needs to be protected from overdischarge. It supplys power to a Real Time Clock and SRAM ICs when my application is not powered(3.5uA). I was thinking of using a supervisor chip that cuts out at 2.0V to protect the battery from discharging below its 2.0V minimum specification. The supervisor can cut power to the RTC and SRAM but then I need to disconnect the supervisor from the coincell. I found supervisors that use ~2uA typical. adding the supervisor would about halve the life of my battery but may be necessary. Once my circuit is powered up and the coin cell recharges, through a parallel diode, the supervisor would again supply power to the IC's

The supervisor I was looking at is NCP304LSQ20T1G.

Any suggestions on how to disconnect the supervisor from the battery or another novel method not using the supervisor to disconnect the battery from the ICs?

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    \$\begingroup\$ NCP304LSQ20T1G is an Obosolete part, so by that alone, it's not a good choice. \$\endgroup\$
    – MrGerber
    Commented Aug 20 at 17:06
  • \$\begingroup\$ Yes thanks for the comment. I see that the TPS3840 will work as well and better. \$\endgroup\$
    – user30884
    Commented Aug 21 at 11:27

3 Answers 3

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You can just use a more power-efficient supervisor circuit such as the TPS3840PL20DBVR which draws around 250nA typically (and even less as you drop below the cutoff voltage for the cell).

enter image description here

You can probably leave that connected to the battery without adding to the internal self-discharge current very much.

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    \$\begingroup\$ This solution looks like the most straight forward solution and least likely to have a "gotcha" waiting for me. I can select a component that is rated at 2.2V and have .2V as a buffer that drains at the 250nA . Thanks Spehro. \$\endgroup\$
    – user30884
    Commented Aug 21 at 11:36
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A weak feedback with a 74AUP2G04 can be used as a low power latch. If you select them carefully, the operating current beats the spec quite well usually. So the latch can be permanently connected to the battery. The latch output would control the gate of a logic level mosfet. The latch would be cleared by the monitor IC.

Alternatively, the logic-level mosfet used as the power switch can have a weak pull-up or pull-down on the gate. It will then self-latch in the off state. A 10MΩ gate bias resistor would be a good starting value, but you can go up. Once the switch is turned off, there is no current driving the gate anymore, thus no current through the bias resistor. The leakage currents of the mosfet would be the only load on the battery.

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  • \$\begingroup\$ This is interesteing I will have to check some of the parameters and see how robust the solution would be accounting for part variability. \$\endgroup\$
    – user30884
    Commented Aug 21 at 11:31
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You could use the output of the NCP305LSQ20T1G (with the open-drain output) to control a logic-threshold, high-side P-MOSFET and shutoff the power to everything including the NCP305LSQ20T1G. (The NCP304LSQ20T1G, with the complementary output, would turn on the control MOSFET when unpowered through the output P-MOSFET).

With the open-drain output you will need a large resistor (e.g. 10MΩ) from the source to gate of the MOSFET to control the MOSFET.

But you would need a momentary "start" push-button switch across the MOSFET to initially energize the circuit after the battery is charged, since the circuit won't power up otherwise.

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  • \$\begingroup\$ I won't be able to add a push button. There may be a way to use a FET to re-engage the battery circuit with a momentary FET switch at power up. This looks like it needs more fleshing out. \$\endgroup\$
    – user30884
    Commented Aug 21 at 11:33

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