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I'm working on a design where I have a need to generate about 10A at 5V across a long bar-shaped board. This is generated from an incoming 12V DC rail. For a number of reasons (physical constraints, thermals, EMI) it makes more sense in my application to use multiple smaller buck converters rather than one large one, producing separate 5V rails for different physical regions of the board. For the purposes of this question, let's assume four buck converters.

I'm looking at buck converters in the 1.5-10MHz switching frequency range. These almost invariably come with a SYNC pin which allows their switching frequencies to be synchronised by an external clock driver. Some of these converters also support spread-spectrum clocking when they are not being synchronised. These features are helpful for mitigating EMI issues and improving PDN integrity.

It appears to me that there are two potential options here.

Option A is to use an external clock generator IC with spread-spectrum support, and generate four clock outputs from that. Ideally these clocks would be shifted 90 degrees in phase to minimise dI/dt on the upstream 12V rail, but the cheaper clockgen options (e.g. Si5351) often don't support that much timing skew control at lower frequencies; as a result the clock phases might be at something like 0°, 45°, 180°, 225°, but this seems generally fine. The clockgen can then be configured for spread-spectrum, e.g. ±1% center spread at ~30kHz rate. All converters operate at the same frequency at any point in time, since the spread-spectrum is global.

Option B is to not synchronise the converters, and use converters with their own spread-spectrum feature. Since nothing is synchronised and all the converters are shifting their switching frequency over time, there will be constant drift. Any overlap between switching edges will be minimised by the pseudorandom behaviour of the system. The converters can also independently adjust their own switching frequency as needed.

Assuming that the cost is roughly equal, what are the pros and cons here?

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  • \$\begingroup\$ Do you know that an EMI issue exists in the first place? Is this a particularly demanding application (say, 20dB+ below commercial levels?), or is layout expected to be too challenging (congested design, narrow board, etc.)? \$\endgroup\$ Commented Sep 8 at 6:50
  • \$\begingroup\$ @TimWilliams It's a long narrow board with a fairly dense layout, and there will be a dozen of these boards operating in the same environment. I also take pride in the robustness of my designs and would prefer to over-engineer EMI reduction than save a few hours and cents. That said, even if I didn't strictly need synchronised clocks here, the question stands by itself as a matter of good practice. \$\endgroup\$
    – Polynomial
    Commented Sep 8 at 10:59

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I would prefer a fixed phase relationship between the converters. In this case the bulk capacitors on the 12 V input side never must provide the higher current of multiple converters switching randomly at the same time.

EMI filtering is simpler, because the noise bandwidth is much smaller.

It may be an issue to route all these clock lines along the bar. You could place a chain of inverters, say 6 gates from a 74HC14 or a single 74AHC1G17 with R/C delay at the input, between the converter sync inputs. This will also produce a fixed phase shift using only one clock signal.

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I ended up talking this through with some folks who do a lot more power electronics than I do, and they pointed me in the right direction: option A.

There are two key problems with option B: beat frequencies and unintentional synchronisation.

If you run multiple buck converters with independent spread-spectrum clocks, there will be intermodulation between the nearby frequencies. This will create a beat frequency at the delta between the frequencies - in this case, in the range of 0-250kHz. These frequencies are far harder to filter out than the MHz range.

In addition, it is possible for the buck converters to unintentionally track each other rather than operate psuedorandomly due to mutual crosstalk overriding the normal variations in component values and parasitics. They may settle in-phase with each other under relatively constant current load, then slip back out of phase after a perturbation. This leads to more complex EMI behaviours and increased ripple current on high-side rail capacitors.

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  • \$\begingroup\$ Well, "will" is a strong word. Could be. Depends how the regulators respond to their environment. I would just as well guess they'll ignore external sync and go on their merry way, most likely being completely incoherent -- that leaves the catch, maybe they randomly sync, because the control does actually depend on environment (e.g. VCC noise), or they just start up in sync and happen to have perfectly matched clocks. But we can't know for certain whether either outcome is true. The advantage of A is not so much electrical, but the design assurance of avoiding the above uncertainty. \$\endgroup\$ Commented Sep 8 at 6:52
  • \$\begingroup\$ @TimWilliams I'm not sure where you got "will" from regarding them syncing. I said "it is possible". And yes, the issue on that front is a lack of confidence on the behaviour. \$\endgroup\$
    – Polynomial
    Commented Sep 8 at 10:49
  • \$\begingroup\$ "They" did -- "there will be intermodulation" \$\endgroup\$ Commented Sep 8 at 18:29
  • \$\begingroup\$ @TimWilliams Yes, there will be intermodulation of the upstream currents, leading to beat frequencies. That's unrelated to the paragraph about tracking each other, which may occur. \$\endgroup\$
    – Polynomial
    Commented Sep 8 at 18:30
  • \$\begingroup\$ No, in general there will not -- the upstream path will most likely be linear and currents superimpose without mixing! (But you see a certain tension here: there's only so much critique that is worth bringing upon an unsourced, unattributed quote; but yet it stands prominently in plain view. The source will never see this feedback, and you don't deserve that criticism since it's not your words.) (Put another way: I don't know whose misunderstanding it is; though since this point apparently wasn't obvious, it turns out to be useful to point out.) \$\endgroup\$ Commented Sep 8 at 18:32

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