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I will need to communicate with a device using serial protocol mostly similar to SPI but with several changes:

  • Data packet can has any bit length (e.g. 35 bits)

  • Stop sequence formed by lack of clocks for time more than needed to transmit 2 data bits

I could handle this by software implementation of this protocol, but the communication frequency is 40 MHz (20 Mbits/s) so I will need pretty fast controller to handle this.

Now I'm looking for two possibilities:

  1. Use the controller having more flexible SPI (I don't even know where I could look for it, if any of AVR will fit my needs I will be happy).

  2. Attach a hardware shift register to general purpose controller (most likely AVR in my case).

Surely I'd prefer the first option. Any thoughts?

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  • \$\begingroup\$ You might find something from XMOS useful. \$\endgroup\$
    – Ignacio Vazquez-Abrams
    Commented Apr 19, 2015 at 20:07
  • \$\begingroup\$ @IgnacioVazquez-Abrams, could you be more specific? XMOS has lots of families so I'd be very appreciate if you will give me a hint. \$\endgroup\$
    – Roman Matveev
    Commented Apr 19, 2015 at 20:12
  • \$\begingroup\$ Any of them. You only need maybe 2 cores to do this so anything they have should work. \$\endgroup\$
    – Ignacio Vazquez-Abrams
    Commented Apr 19, 2015 at 20:20
  • \$\begingroup\$ Pete from XMOS here, yes I reckon we could definitely help with this challenge. You don't need to go to the expense of an FPGA and you can programme 10ns resolution in 'C'. Is the spec for the protocol written up anywhere ? What else do you need your micro to do ? best, Pete \$\endgroup\$
    – Pete Tasker
    Commented Apr 30, 2015 at 10:29

1 Answer 1

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SPI peripheral inside a general purpose microcontroller (AVR, or PIC, or MSP40, etc) is hardwired to a large extent. It is what it is. Transaction stop sequence is formed by the CS# line.

Want to use a non-standard SPI-esque communication format with framing bits? I think, it would be safe to assume that there isn't a general purpose microcontroller (μC) with a flexible enough SPI peripheral that can support that.

Probably, a good bet would be to use programmable logic (similar to your idea about external shift register). You could program a CPLD (or FPGA) to convert from non-standard SPI-esque protocol to normal SPI, then a general purpose μC would read the data through normal SPI. There are also Cypress PSoC microcontrollers with built-in CPLD fabric.

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    \$\begingroup\$ While the SPI specification doesn't actually enforce a bit length, as Nick said, most uC manufacturers will have a fixed byte length. PSOCs would be a good choice, also look at XMOS microcontrollers, where everything is controlled using software (and therefore configurable) using their multicore microcontrollers. \$\endgroup\$
    – Joel Gibson
    Commented Apr 19, 2015 at 20:43
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    \$\begingroup\$ I'm certain that a small CPLD like the CoolRunner2 XC2C64A should easily able to convert such a protocol to proper SPI. These cost about 3 bucks in volume, so they aren't that expensive either. \$\endgroup\$
    – Nils Pipenbrinck
    Commented Apr 19, 2015 at 22:43
  • \$\begingroup\$ Thank you,@NilsPipenbrinck for pointing me to the particular device! \$\endgroup\$
    – Roman Matveev
    Commented Apr 20, 2015 at 5:25

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