I've seen circuit diagrams that use a polarize electrolytic to remove DC offsets from an input audio signal.
The cap is polarized. Why is this ok?
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\$\begingroup\$ Can you show an example circuit? \$\endgroup\$– endolithCommented Apr 12, 2010 at 15:09
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2 Answers
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As long as the DC level is positive, the AC amplitude of the audio signal is of no consequence because it is a "coupling" capacitor, in the sense that the RC time constant is much higher than the highest 1/f of the audio signal (excluding dc of course), so the capacitor never gets "charged up" to the audio ac signal voltage (only to its dc value). Instead, the voltage across its terminals remains approximately constant. In other words, the capacitor rides with the input, and if the RC constant was not high enough, audio would be distorted. For example, you could have 1V of dc offset and 10V of ac amplitude. If RC is high enough, the voltage accross the capacitor will ALWAYS be very near 1V,NOT 11V to -9V as the comment to the first answer seemed to imply. Hope this helps.
answered Apr 12, 2010 at 17:42
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\$\begingroup\$ Mea Culpa. I was thinking about the problem incorrectly. I have deleted the original comment where I incorrectly stated a problem about capacitive coupling. Thank you for pointing this out. \$\endgroup\$– W5VOCommented Apr 12, 2010 at 20:52
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\$\begingroup\$ The argumentation about RC constant is wrong. In the passband of the RC filter, the capacitor is absolutely being charged and discharged in both polarities. Do the math with an example. For instance low pass filter with 0.1μF and 1000 Ω. The knee frequency is around 1600 Hz. The RC time constant is .1 ms. See? The charge time/speed is in the ballpark of the oscillation frequency range. It cannot work otherwise: a cap cannot pass AC without being charged and discharged both ways. \$\endgroup\$– KazCommented Nov 9 at 7:22
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\$\begingroup\$ So indeed, if the coupling capacitor is used between two DC domains such that the transmitted signal's displacement voltage (zero to peak) exceeds the voltage difference, then the electrolytic will go into negative territory. It's just a question of how much. They can tolerate some of that. We can often design for it not to happen: e.g. signal swinging around 1V coupled into a 5V bias (4V displacement), where the amplitude stays well within 4V. \$\endgroup\$– KazCommented Nov 9 at 7:27
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Why wouldn't it be ok? In the usual configuration, the DC voltage on the positive side of the cap is always higher than the DC voltage on the negative side.
Even if you connect it with no bias, electrolytics can still withstand a small reverse voltage. It's only after they are reversed continuously at 1 V or more that the dielectric starts to degrade. See http://en.wikipedia.org/wiki/Electrolytic_capacitor#Polarity http://en.wikipedia.org/wiki/Capacitive_coupling
