Reduced output of op amp peak detection and hold circuit

Question

I have used op amp peak detector & hold circuit for finding the peak of voltage obtained from scintillation detector and pre-amplifier.

I observed that the observed peak and hold output was 700 mV, instead of the expected 1.5V and that when the pre-amplifier was connected to the peak and hold circuit, the portion of the pre-amplifier output waveform above 700mV was clipped. For debugging the issue, the following points were checked:

1. The Op-Amp circuit is not loading the source by drawing excess current.
2. Op-Amp slew rate is 125 V/us and that the rate of charging the capacitor with 1uF cap and 100 mA short circuit current is 100 V/us. The detector pulse rises from 0 to 1.5V in 100 ns, so rate required is 15V/us
3. A 20kHz triangular wave with 1.7V was provided to the peak-hold circuit. The peak-hold output was 1V and the input triangular wave was clipped to 1V pk-pk. SPICE simulations show similar, but less severe results. The effect is least if the input is a square wave or the frequency is least.
4. The circuit works for DC input (provide 3.3V and disconnect it, the capacitor voltage started falling from 3.3V)

All the above observations have been done with nMOSFET in open-state.

Can any one tell me where am I going wrong in the design?

Answer 1

You have two errors which impact your 20 kHz simulation.

The first is your hold capacitor. At 1 uF, a 15 V/usec slew rate requires a charge current $$\frac{dV}{dt} = \frac {i}{C} $$ $$i = C\times \frac{dV}{dt} = 10^{-6}\times 15\times 10^6 = 15 \text{ amps} $$ and there is simply no way you'll get that out of an AD825. A 20kHz, 3.4 volt triangle wave requires $$ \frac{dV}{dt} = 2\times3.4\times2\times 10^4 = 1.3\times 10^5\text V/\mu sec$$ This is about 100 times less than the pulse requirement, but it's still too much for the AD825. If you pay close attention to the output of your simulator, you'll see the reason the output is low is that the output noticeably lags the input, and the hold capacitor stops charging while the voltage is too low.

You can see that the output (red) does not charge fast enough to follow the input (green), and the output levels off when the input drops below the output. In other words, the peak detector is working as well as it can given the slow response at the capacitor.

The answer is simple: reduce your hold capacitor. A 1 nF will work very nicely on your circuit.

Once you do that, you'll see a new problem: droop on the output. This is also pretty simple. When you set up your simulation, you used the default iN1183 diodes, and even by 40 year old standards the 1183 is pretty crappy. Specifically, its reverse bias current is horrible. Replace the diodes with 1N4148s and see how you like that.

Now change your simulation input to a 100 nsec pulse, and be disappointed. The capacitor overcharges and once that happens you have no way to discharge it other than using the FET. Reducing the hold capacitor still further will reduce the problem, but it is an artificial solution, and will not work reliably if the input pulse width or amplitude vary. Your problem is simply that the AD825 is too slow to handle 100 nsec pulses in this configuration. Although the data sheet shows it settling acceptably for amplifying 100 nsec pulses, that is not what you are doing. Between the time delay associated with charging the hold capacitor and the intrinsic delay caused by the second AD825, you simply cannot accurately do what you want with this op amp.

EDIT - Also, just for fun, try changing the hold capacitor to 100 nF, to see that this is not a simple amplifier.

Answer 2

This is only a suggestion. Why don't use a sample/hold component as LF398 ? It make all the job. Add only a capacitor. Less than 10-μs Acquisition Time. If too slow, there is other components much more faster. You can also use a ADC, like flash converter. 1 us conversion time or faster.