Need help understanding this circuit (with LUTs, multiplexer and flip-flops)

Question

The exact question is the following:

For the programmable logic block shown in Figure 5-13, show the necessary configuration settings to implement each of the following types of circuits. You can assume that the upper data input of each multiplexer is chosen with a select input of 0. (a) A combinational function of inputs a, b, and c. (b) A Moore machine (c) A Mealy machine

Figure is the following:

When it asks for the combinational function, I think it is asking about the truth table. And from that I can draw the moore and mealy machines too. But the problem is that I'm unable to figure out the outputs of the two LUTs. There are 4 combinations of inputs possible for each but what is the output value of each of those inputs? I'm also unable to figure out the meaning of the vertical line in middle of the dotted box (labelled as addition logic). Any help is appreciated.

(The question is from the book "Logic and Computer Design Fundamentals page number 321, 5th edition)

Answer 1

From the problem statement:

show the necessary configuration settings to implement each of the following types of circuits.

The points of concern, then, are the configuration values 0 through 10. However, the controls 0 through 7 are the values to implement the logic functions of the two 2-LUT blocks. Thus, the question is referring to the values to choose for controls 8, 9, and 10.

When it asks for the combinational function, I think it is asking about the truth table.

You do not need the complete truth table. Because the functions implemented by the 2-LUTs are arbitrary, you cannot determine the truth table. However, you can examine the configuration of the multiplexers to implement a combinational function. Notice that the input c can control MUX1 if control 8 is set to 0. This allows a 3-input logic function to be implemented, using both 2-LUT outputs. The implemented function would be \$f_{mux}(f_{LUT_1}(a,b), f_{LUT_2}(a,b),c)\$, which, in binary, covers all possible 3-input logic functions.

I'm also unable to figure out the meaning of the vertical line in middle of the dotted box (labelled as addition logic).

The addition logic box is mostly irrelevant to these questions. The vertical signals are actually labeled: carry_in and carry_out. The dedicated logic for adders improves the efficiency in using the logic block in a wide adder. That logic is selected by control 9 being set to 0. Likely, that is not required, so you want control 9 to be set to 1 to only use the MUX1 output.

Differentiating the Moore and Mealy implementations in exactly one logic block is also done through control 8. With a value of 1 at control 8, the output of the register can feed back to be a term in the combinational logic, acting as the third input by controlling MUX1.

Completing the solution to any of the three parts requires choosing the value for MUX4 as appropriate for the logic or state machine implementation.

Answer 2

I think the misleading part about this question is that it has several different constructs to implement logic, most of which are irrelevant to solving the question. It's all about having the correct routing. The LUTs can be considered a block of logic, the summation/carry block could be considered a block of logic, even a straight connection could be considered a block of logic (smallest truth table ever).

Check out these diagrams of the 3 parts of the question and see if you can envision how the muxes would need to be configured to allow the data to flow.