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The table in the bottom image is the solution for an exercise based on a NAND SR flip-flop.

"Complete the truth table for the SR flip-flop."

The "initially" row is given, and I was supposed to fill in the q and Q-bar values for the remaining rows. I don't understand the solution - why does changing S to 0 result in Q switching to 1? And why does switching S and R to 0 result in Q = 1 and Q-bar = 1?

From my very limited understanding so far in this topic, I would have thought that applying 0 to S would leave Q and Q-bar unchanged, as S stands for "set" and we are not applying a current.

Any help much appreciated.

enter image description here

Solution:

enter image description here

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  • \$\begingroup\$ i think this will help electronics.stackexchange.com/questions/163164/… \$\endgroup\$
    – User323693
    Commented Dec 31, 2019 at 9:03
  • \$\begingroup\$ Do you now how NAND gate work? If any input of the NAND gate is set to LOW the gate output will be at HIGH state no matter what. And your RS F-F is build using the NAND gates. So why should the NAND gate behave differently in the case? And to get a LOW state at the output you need to set all the inputs of a gate to HIGH state \$\endgroup\$
    – G36
    Commented Dec 31, 2019 at 10:04

2 Answers 2

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You are making an assumption that might not be valid. You are assuming that forcing S high sets the latch...it's possible that S is active-low, and that a low value on S actually represents the SET input condition.

The key to understanding these latch circuits is to remember how a NAND gate works. The output of a NAND gate is low if and only if both inputs are high. If either input is low then we know that the output must be high, regardless of the value of the other input.

So, if S=0 then Q must be 1. If R=0 then Q-bar must be 1. If both S and R are low then both Q and Q-bar must be 1.

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  • \$\begingroup\$ But we could swap S input with the R input to get active-high SR flip-flop. \$\endgroup\$
    – G36
    Commented Dec 31, 2019 at 16:04
  • \$\begingroup\$ @G36 But if you do that then the "hold" input condition is when S=R=1 which doesn't make much sense. The typical NAND latch has active-low inputs. \$\endgroup\$
    – Elliot Alderson
    Commented Dec 31, 2019 at 16:10
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why does changing S to 0 result in Q switching to 1?

Sketch up the truth table for a single NAND gate. You will see that the output of the NAND gate goes high only when both inputs go low.

And why does switching S and R to 0 result in Q = 1 and Q-bar = 1?

This state of the S/R NAND latch is not allowed. According to the truth table of the single NAND gate, Q=1 and Q-bar=1 is the actual output of the circuit, but as the outputs shall be inverted to each other, this is not allowed.

BTW: This has nothing to do with a SR-flip-flop. This circuit is called a latch instead, because it is an asynchronous circuit.

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    \$\begingroup\$ In my field (HDL design) this is NOT called a latch. \$\endgroup\$
    – Oldfart
    Commented Dec 31, 2019 at 11:38
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    \$\begingroup\$ In my field (VLSI design) this is called a latch. The term "flip-flop" is reserved for edge-triggered storage elements. \$\endgroup\$
    – Elliot Alderson
    Commented Dec 31, 2019 at 14:51

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