0
\$\begingroup\$

All of the digital communication protocols I know, are built on the principle of the minimum distance, error detection and error correction.

There are some protocol able to detect and or correct "shift errors" in the time acquisition, i.e. the error of acquiring twice the same bit because a mismatch of the clock rates?

\$\endgroup\$
  • \$\begingroup\$ All of them? After all, decoding a stream of symbols implicitly requires determining where the symbol boundaries are, and every protocol includes some means of doing so. For example, in ordinary asynchronous serial (UART) protocol, all timing is relative to the leading edge of the start bit. What is your actual question? \$\endgroup\$ – Dave Tweed Sep 7 '17 at 15:00
1
\$\begingroup\$

Quasi-synchronous Digital communication over a carrier depends on the channel characteristics and the codec used as well that the clock must be synchronized to the data for symbol clock, bit clock, byte clock, frame clock and message number.

When clock sync is not achieved with adequate margin, there is always a statistical tradeoff between signal level, noise floor and thus CNR and decoding to bit SNR vs BER. While some are more resistant to Ralleigh Fading, Rician Fading and Doppler shift, none can overcome ambiguity of clock sync. Thus phase received signal strength indicator , RSSI and Phase detector jitter are indicators of expected BER and if exceeding the timing window margin will result in a bit error. FEC sacrifices the channel capacity for redundancy to enable extending the range of RSSI to BER to extend the curve.

The unknown transient effects of Doppler shift or fixed carrier with frequency error and transient PLL response can be controlled but also has a tradeoff for noise bandwidth and response time. There are many algorithms to flash detect phase error and correct if the SNR is high enough, but in low SNR situations may add to the jitter.

For example in all modems, there exists a preamble to synchronize and compensate the receiver for channel equalization and bidrectional training to optimize bit rate and BER, but not means to correct clock phase bit errors before synchronization is detected.

Synchronization bit patterns using many methods including shift patterns design around autocorrelation energy distribution functions are common as well as others for trellis coding to improve sync acquisition time. But no amount of coding can correct a bit error before clock/ bit/frame sync is achieved.

I believe you are wondering how are synchronization patterns generated and how can they be improved in the last 50 years of R&D, which has developed new channels.

It all depends on the channel if fixed or mobile and the tradeoffs between range, power, cost, and channel capacity.

Vertical recording HDD's use quite different RLL encoding with very powerful FEC block coding from RF channels due to the SNR and channel characteristics.

We are ignoring asynch communication for this question.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.