Why doesn't voltage drop across this resistor when transistor is off?

Question

The following excerpt from a book explains the functioning of the circuit below:

When V_in < V_th (device threshold voltage), the supply voltage (V_dd) is measured at the outlet. When V_in is increased above V_th, the NMOS turns on and V_dd is now dropped across the load resistor; V_out is now in common with ground, and the signal at V_out is inverted relative to V_in.

Question: Why is V_out = V_dd when the NMOS transistor is off (i.e. when V_in < V_th)? With the transistor off, it seems we should effectively be able to ignore that part of the circuit and compute V_out using Ohm's law to predict the drop of V_dd across the resistor. Why is this not the case?

Answer 1

From the comments:

... but I am not sure why the book would be assuming no circuit connected at V_out. This section of the book is talking about integrated circuits (and said this circuit was commonly used in IC's after 1980). It would therefore seem safe to assume that there will always be another circuit attached so that V_out of this circuit is V_in of some other circuit. Do we know that this won't change the circuit behavior "too much"? That is, do we know that this voltage inversion switching will still work if we add another circuit onto V_out?

This is actually a fair assumption for MOS if they are driving other MOS devices.

Figure 1. The output (1) of one gate typically drives the inputs (2) of other gates and these have a very high input impedance.

Note that this will really only be true in the steady state condition. When switching occurs then the input gate capacitance has to be charged via the V_dd resistor and a voltage drop will occur as you suspect. It is this switching power dissipation that generates much of the heat in high-speed logic.

Answer 2

Think of the transistor as having a very large resistance when OFF. So you essentially have this:

^{simulate this circuit – Schematic created using CircuitLab}

The current is then:

$$ I=\frac{V_{DD}}{R_D+R_{off}}$$

And the voltage across \$R_D\$ is:

$$V=IR_D $$

What happens if \$R_D\$ is very large (say 10M\$\Omega\$)? The current is essentially zero then, and the voltage across the resistor is 0V.

In the ideal case, \$R_{off}\$ is 'infinite' which would mean you'd have an open circuit and no current flows through an open loop. But even for practical values, \$R_{off}\$ forces the current to be negligible.

If there were some other circuitry connected to \$V_o\$ in your schematic, then we'd need to know the equivalent resistance looking into that other circuit because the current may no longer be negligible, but in your case, it is unloaded at \$V_o\$.

Answer 3

You can use Ohm's Law, but you have to recognize that if the transistor is not conducting then no current flows through the resistor. Therefore, there is no voltage across the resistor, which means that the voltage at both ends of the resistor must be the same. Since we know that one end of the resistor is connected to \$V_{DD}\$ then the other end must also have a voltage equal to \$V_{DD}\$. So, when no current flows it must be true that \$V_{OUT}=V_{DD}\$.

Answer 4

Because if nothing is connected to Vout the resistance of air is roughly 10^9Ω, so it forms a resistive divider with the air. Even a 1MΩ resistor will be insignificant compared with that of air the equation for a voltage divider looks like this:

$$\frac{10^9}{10^9+10^6}=0.999$$

In all odds you'll probably have something lower than a 1MΩ resistor there, so you won't even notice the voltage drop. If you measure this with a meter, it will also be high impedance so you'll get a similar result.

Answer 5

When the NMOS is off the resistance of NMOS is very high and the current is very less between . You can intuitively think as if the the transistor is not present in the circuit and hence you can think of it as an open circuit between the ground and the resistor end.

Hence the circuit becomes something like this.

^{simulate this circuit – Schematic created using CircuitLab}

As we know there is no current in the resistor, it acts like a normal piece of wire, essentially shorting \$V_{dd}\$ and \$V_{out}\$. This is why you see \$V_{dd}\$ at \$V_{out}\$ when the NMOS is off.

The effective circuit at zero load becomes like this

^{simulate this circuit}

Note: The above circuits are drawn only for intuitive understanding and in reality a very small amount current flows through the resistor and the NMOS (which may be viewed as a high resistance instead of a open circuit) to the ground.

Answer 6

Question: Why is V_out = V_dd when the NMOS transistor is off (i.e. when V_in < V_th)? With the transistor off, it seems we should effectively be able to ignore that part of the circuit and compute V_out using Ohm's law to predict the drop of V_dd across the resistor. Why is this not the case?

"It is the case." You are correct.

Except you show no load for a voltage divider to perform KVL, that's all.
When MOSFET is off and may be removed.