# Why is the Digital 0 not 0V in computer systems?

I'm taking a computer system design course and my professor told us that in digital systems, the conventional voltages used to denote a digital 0 and a digital 1 have changed over the years.

Apparently, back in the 80s, 5 V was used as a 'high' and 1 V was used to denote a 'low'. Nowadays, a 'high' is 0.75 V and a 'low' is around 0.23 V. He added that in the near future, we may shift to a system where 0.4 V denotes a high, and 0.05 V, a low.

He argued that these values are getting smaller so that we can reduce our power consumption. If that's the case, why do we take the trouble to set the 'low' to any positive voltage at all? Why don't we just set it to the true 0 V (neutral from the power lines, I guess) voltage?

• I think the simplest explanation is that there are parasitic resistances in wires/traces/"switches"(transistors) so you would never really reach 0V, therefore you need some margin. As technology gets better, the margins can get tighter. Commented Sep 11, 2019 at 10:09
• Logic has never had absolute single values for high and low; TTL has an absolute range and pure CMOS has a range defined by the power rail. Commented Sep 11, 2019 at 10:15
• The low limit has never been 1v, checkout Andy's answer which states it's 0.4v or 0.8v depending on whether you're sending or receiving (talk accurately, listen forgivingly) Commented Sep 11, 2019 at 11:32
• The voltage you're quoting is the upper bound (threshold) for a logic zero. Commented Sep 12, 2019 at 2:37
• There is no such thing as 0 V, only in a perfect world do we speak of it.
– Mast
Commented Sep 12, 2019 at 8:17

You are confusing the "ideal" value with the valid input range.

In usual logic, in ideal conditions, the logical zero would be precisely 0V. However, nothing is perfect in real world, and an electronic output has a certain tolerance. The real output voltage depends on the quality of wires, EMI noise, current it needs to supply etc. To accommodate these imperfections, the logic inputs treat a whole range of voltage as 0 (or 1). See the picture in Andy's answer.

What your lecturer probably meant by 0.75V is one of the points making the logical 0 range.

Note there is also an empty range between 0 and 1. If the input voltage falls here, the input circuit cannot guarantee proper operation, so this area is said to be forbidden.

You are getting confused. Look at TTL for example: -

A low input level is between 0 volts and some small value above 0 volts (0.8 volts for the case of TTL).

why do we take the trouble to set the 'low' to any positive voltage at all?

We take the trouble to ensure it is below a certain small value.

Picture from here.

• To expand on this, the valid input voltage ranges are different for TTL signalling versus CMOS versus LVCMOS signalling. The reason for this is that TTL logic (and the compatible NMOS that followed it) had a lot more difficulty pulling up to the positive rail than down to ground. Modern CMOS logic can pull equally well either way, and it's easier to build a CMOS input stage symmetrically as well. A CMOS output will happily drive a TTL input, but you must use special TTL-compatible inputs with a TTL output. Commented Sep 14, 2019 at 9:23
• There's a good and detailed explanation on this subject from TI, here: ti.com/lit/an/scla011/scla011.pdf Commented Sep 14, 2019 at 9:26

It is impossible to produce true zero volts logic signalling. There must be some tolerance allowed for, as the circuitry is not infinitely perfect. Spending money trying to make it infinitely perfect would not be a good investment of design funds either. Digital circuitry has proliferated and advanced so fast because its uses huge numbers of copies of the very simple and tolerant circuits that are logic gates.

The binary states 1 and 0 are represented in digital logic circuits by logic high and logic low voltages respectively. The voltages representing logic high and logic low fall into pre-defined and pre-agreed ranges for the logic family in use.

The ability to work with voltages within these ranges is one of the primary advantages of digital logic circuitry - it's not a failing. Logic gate inputs can easily distinguish between logic high and logic low voltages. Logic gate outputs will produce valid logic high and low voltages. Small signal noise is removed as logic signals pass through gates. Each output is restoring the input signal to a good logic voltage.

With analogue circuits, it is between more difficult and practically impossible to distinguish noise from the signal of interest and to reject the noise entirely.

• Very sharp thresholds (without hysteresis) also mean ridiculously high gain amplifiers. Also known to be ridículously feedback and oscillation prone, drift prone, and generally nervous. Commented Sep 11, 2019 at 20:27
• Also note that logic 1 and 0 can be usefully represented as low and high voltages respectively where it makes more sense for the circuit to do so. Indeed, signals like global resets are traditionally active low, and in the nmos era (A technology that was notoriously bad at pulling up) and to a lesser extent the TTL era (same issue) it was common to male IO active low just because that was the only way to actually get any current to flow. Commented Sep 11, 2019 at 23:47
• Also of note is current-mode logic where logic values are defined in terms of current rather than voltage. This allows for faster switching and better noise tolerance in transmission (because of Kirchhoff's current law) at the cost of increased power usage (though Wikipedia claims that picoamp CML has been achieved, so that wouldn't be an issue either). Commented Sep 13, 2019 at 21:48

Additionally to the points that is made by the other answers, there is the issue of parasitic capacities at high switching speeds (the usually ignored capacitance of wires and other components). Wires usually also have a slight resistance. (A very simplified model!)

simulate this circuit – Schematic created using CircuitLab

Being an RC network, this results in an exponential falloff curve ( V ~ e^-kt ). If the receiver sets it threshold very low (near 0V) then it would have to wait a significant time for the output voltage drop enough to trigger the threshold. This time might seem insignificant, but for a device supposed to switch a million (billion even) times a second, this is a problem. A solution is to increase the "OFF" voltage, to avoid the long tail of the exponential function.

Because nothing is perfect and you need to provide for this with a margin of error. Those numbers are thresholds. If the lowest possible voltage in your system is 0V and your threshold is 0V, where does that leave you if ALL your components and wiring aren't perfect conductors (i.e. always have some voltage drop) and noiseless in a noiseless environment? It leaves you with a system that can never output 0V reliably, if it can even do it at all.

In a 2 rail system (usually chips powered with just a single positive voltage plus ground), whatever switch or device is pulling the output capacitance down to a low signal level has finite resistance, and thus can’t switch a signal wire to zero Volts in finite time. (Ignoring superconductors). So some realistic lesser voltage swing is chosen which meets performance requirements (switching speed vs. power requirements and noise generation, etc.)

This is in addition to margins needed to cover ground noise (different ground or “zero” voltage levels between the source and destination circuits), other noise sources, tolerances, and etc.

Contrary to some responses here I'm pretty sure that there has been such a thing as a pure 0V low in the past. Relay logic! I don't think we want to go back to that though!

• Did your relays use superconductors? I don't think so. Commented Sep 12, 2019 at 14:39
• +1 because of unfair criticism. A pure 0V can be easily achieved. It can almost be achieved with a relay and simply with access to devices connected to negative supplies and feedback if desired. That it has been used as a required design value for digital communications does seem unlikely though but that should not be reason to down vote this answer. Commented Sep 12, 2019 at 22:13
• @ElliotAlderson No I cannot, I specifically wrote that it was unlikely to exist which means I have no way to prove that it does. However can you prove that such design value has never been required? I didn't think so. Now go and give the new guy an up vote (to get it back to zero) so he does not get demoralised by nitpicking and go away and we loose one more bright (young) mind because of no good reason. Commented Sep 13, 2019 at 8:13
• @ElliotAlderson I think that if you put a scope on a real relay coil, you would see the voltage go through zero on its way to a largeish negative value when the contacts open. But, it's unclear to me whether you're talking about a real circuit, or an ideal circuit. Do ideal contacts arc? If not, then the voltage must go to negative infinity. In any case case, after the contacts have opened and the arc is extinguished the resistance in the ideal circuit will be infinite. Not sure what that does to your time constant. Commented Sep 13, 2019 at 14:04
• @SolomonSlow The transient behavior is real but it is easily modeled with an ideal circuit. The resistance that controls the behavior of the coil voltage after the contacts open is the resistance of the coil itself (giving you the benefit of the doubt that there are no leakage currents of any kind). It's a parallel RL circuit at that point, which requires infinite time for the inductor current to fall to exactly zero. Even in the practical world, there is some time when the voltage across the coil is non-zero but the relay's contacts become open...a logical '0' with non-zero voltage. Commented Sep 13, 2019 at 14:12

The simplest answer is that all semiconductors used for digital logic outputs have some voltage drop across the two output electrodes, that there are practically always some stray currents, voltages and noise present on a line, in a circuit or at an input, and that waiting for an output or input to fall to absolute 0.00V makes a logic circuit slower. Those issues have been steadily reduced as components and circuits got improved over the years, which has allowed decreasing the logic voltage levels and ranges while increasing speeds and decreasing power requirements, but they can't be completely eliminated, and thus some headroom needs to be allowed to counter them. In an ideal world, a logic zero would be 0 volts, but an ideal and a practical/real world are not the same thing.

For BIPOLAR transistors like the NPN type used in the common emitter configuration, the voltage across the collector-emitter practically never reaches zero, and can be anywhere from 0.1V to 0.7V, possibly going higher in high speed and high current circuits. With MOSFET transistors, the output voltage comes much closer to 0.0V but it still depends on:

1. the MOSFET channel ON resistance (RDS(ON)), which in very small MOSFETS used in high-density ICs is higher than in high power discrete MOSFETS (which, in turn, are also slower)
2. the current through the drain-source channel
3. the speed of switching the MOSFET on and off

Since the higher speed circuits involve quickly changing the states of the individual elements of a digital circuit and charging and discharging parasitic capacitances, the very fast discharge of such a capacitance generates a high-current pulse which generates a higher voltage drop across a conducting element or a switch.

There is also some noise or voltage drops in the circuits or on the signal lines, which is never at an absolute zero volts, so allowing some level above 0.00V to be interpreted as 0 is necessary to make sure the digital logic circuit doesn't remain stuck at a logic 1 because the input never saw an absolute zero (of 0.00V).

Finally, an important thing that either you don't remember or your teacher didn't mention as a reason why we're going for even lower voltage levels range is that it also allows FASTER switching between the states (between 0 and 1), besides the lower power consumption. Going from 0.2V to 2V will take longer than going from 0.2V to 1V, while also using more energy. Even IF we can achieve 0.00V at a logic zero level AND properly interpret it, it will take a little longer than waiting for some level above 0.00V (like the 0.05V your teacher mentioned) which includes a "settling time" (the time required for the output to reach and steady within a given tolerance band), which will defeat the goal of increasing the logic circuit speeds.

As my practical advice, I recommend you try using a high resolution digital voltmeter (more than 4 digits) and you will see the further you go from the decimal point to the right, the more unsteady those digits become, and you can even measure a small voltage in a short-circuit, due to galvanic junction, stray induced currents or voltages and the inherent noise in the input of the voltmeter or any instrument for that matter. Also, the neutral or zero in power lines is almost never 0.00V, due to circuit currents travelling through it, stray voltages and currents induced in it, or any other factors. Try sticking a piece of metal into the ground and measuring the AC voltage between the ground and the neutral wire, and you will see that it is not really at a zero compared to ground. That will help you understand why an absolute zero is a very rare occurrence in practice.

From a Process Control Instrumentation angle, this BIAS above Zero, is to provide additional info about the integrity of the instrument. If an instrument was calibrated 1V-5V = 0-400 gallons per minute (gpm), then, if 1V was measured by the instrument, you'd know that there was 0 gpm. All would be normal.

However, if 0V were measured, then that would be some kind of alarm condition that the instrument has failed or shorted. A properly programmed control system would throw its respective control loop into manual to prevent slamming the valve either closed or open.

In other words, this BIAS from Zero allows the control system an additional, indirect method to know the health of the measuring instrument (i.e., circuit hasn't Grounded or Failed). If you didn't do this then you might not know if 0V were normal or an alarm condition.

Of course, in the old days, we didn't have all the smart instrumentation that communicates much more diagnostic info. :-)

Update: @Transistor has provided some additional insight, which is much appreciated. For what it's worth, I did realize that there was a digital vs analog conflict in my response (mainly due to the highly technical comments/answers). What I was trying to do was make an 'analogy argument', similar to water pressure vs voltage, to impart a possible reason to not 'just use 0V' as a basis. However, I still may have missed the point. @Transistor, I don't have enough Reputation to Comment, so my question back to you: Should I delete my response? I certainly don't want to mislead. Thanks.

• Welcome to EE.SE. The question is about 5 V digital logic levels rather than analog so I think you have missed the point. From an industrial control perspective it's more like a PLC digital input's guaranteed logic 0 and logic 1 voltages. You can edit to improve your answer. Commented Jul 23, 2020 at 3:58