+1 to using a commercial memory product, but if you want to know the answer...
Yes, there will be some gate leakage. There are various physical mechanisms that contribute to this, but it will never be 0 so long as there is a voltage difference between the gate and either the source or drain.
If you are using a discrete MOSFET, check the data sheet and see if it specs a maximum gate leakage. For example, here's OnSemi's 2n7000: https://www.onsemi.com/pub/Collateral/2N7000-D.PDF
Under Off Characteristics, we have "Gate-Body Leakage Current, Forward", with a max of 10 nA @ Vgs = 15 V, Vds = 0 V.
You can take that current and use it to calculate how fast the capacitor will discharge. For a 1uF cap, 10 nA of current will discharge it at a rate of 10e-9/1e-6 = 0.01 V/s.
Then, for this transistor, the max Vgs(th) is 3.0 V, so if you start at a Vgs of 10.0 V, it will take (10.0 V - 3.0 V)/(0.01 V/s) = 7/0.01 = 700 seconds for the gate voltage to fall beneath the threshold voltage. This is a roughly worst case analysis, because as Vgs falls there will be less gate leakage current, etc. Edit: As someone pointed out, you will also need to account for the self-discharge of the capacitor.
700 seconds may be long enough for your application, or may be way too short. Note also that the transistor characteristics will not stay constant over this time period. You are reducing the Vgs, so the Rds(on) will rise and Ids will fall. (See figure 1)
Note that this discharging process is exactly why DRAM needs to be refreshed, though in that case the capacitor is connected to the drain of a MOSFET, not the gate, but same idea applies.