Why does enabling the clock for port C set the IDR bit 1? It's the configuration for a Nucleo-F767ZI.
The default mode of the pin is as an input, as soon as you enable the peripherals clock (well, a few clock cycles later), the pins state is clocked into the IDR.
Something is making that pin high.
As a comment on your code, there are defines for the bit positions in the registers, probably provided in the same include as you're getting the
RCC pointer from,
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; is more readable than
RCC->AHB1ENR |= 4;