Optimising a single pulse precision peak amplitude detector

So I made this precision peak detector circuit (with reference from EEVblog's video and experimenting with the resistor/capacitor values), with which I want to measure the peak amplitude of a single pulse of width 5us (50ns each rise/fall time at best and 155ns/90ns rise/fall time at worst) and the amplitude is variable and can be within 3mV to 3V. I would like the peak-detector to hold the voltage level for a sufficient amount of time (in this case around 60ms, although I have simulated up to 3s with the same result) without degrading the voltage level too much (a maximum of 1-2mV degradation over 60ms is acceptable for me).

So the result of the above circuit looks good in the simulation. When testing for the extremes I see the following (pics below). Here Green is the final output (voltage at R2), Red is D2 current(essentially to show the peak current the opamp can handle), Blue is the input pulse (V1):

1. For 3mV pulse, here are the results: As, you can see there is a slight offset of around 0.6mV, which is acceptable for me as long it is fairly constant over all my measurements.

2. For 3V pulse, here are the results: Here the peak current in diode D2 (or as I think is a measure of maximum current required from the opamp (U1) is around 79.6mA which is right below LTC6268-10's typical peak output current rating of 80mA.

R2 is basically modeling the input impedance of an ADC which I'll directly connect at the output of U2. I chose LTC6268-10 because of its low input bias current which 'should' help the capacitor to retain the voltage (in this double diode configuration as per the video) for a long time. I would also be using a low leakage analog switch/mux to discharge the capacitor (short it to ground) after I sample it using my ADC.

I need to be as sure as possible that this circuit would work as in simulation (or at least, close enough) before I put it in a PCB.

So my questions are:

1. Do you find any obvious mistakes that I am making here with my component selection (or their values) or the circuit itself? or do you suggest a better circuit to achieve my goal (of measuring peak voltages of a single pulse with an ADC)?

2. In the simulation the capacitor is holding the voltage very very well, which is good but I am thinking if there are any other ways the capacitor could get discharged (in the real world), and what should I take into consideration? Is there a specific type of capacitor, I should go for?

3. Is there a ready-made peak detector IC available already that would perform better than this circuit? I am not looking for S/H IC because I would require precise trigger timing to sample at the middle of the pulse.

4. Since I'll be using SMD components, if you would like, you may suggest anything important that I need to know regarding using SMD diodes, capacitors, etc for this particular circuit.

Side note: If the requirements are too high then I may be inclined to reduce the hold time (currently 60ms) to 6ms depending on the suggestions if that results in a simple circuit.

Thank you so much for reading my post.

Do you find any obvious mistakes that I am making here with my component selection (or their values) or the circuit itself?

Looking at the 1N4148 data sheet, the reverse leakage current is this: -

I know R3 is there to bootstrap the junction of the diodes to reduce leakage current but given that the inherent diode leakage is about 1000 times more than the input bias/offset currents for the op-amp, I would want to make sure that my model and simulation do take this properly into account.

Is there a specific type of capacitor, I should go for?

Ceramics are normally the best choice so I'd go for NP0/C0G characteristics and read the data sheet carefully about what leakages may present themselves.

Is there a ready-made peak detector IC available already that would perform better than this circuit?

It's an off-topic question but I don't know of any.

The 1N4148 is really good on reverse recovery time (4 ns) but make sure you test the diode model with it set to 10 ns just to be sure. There may be some subtle effect here that drains a fraction of a percent of the output voltage on low level signals.

• I have a small question regarding the Op-amp. It seems like the current was limited by the model itself to 79.6mA peak (which you see for the 2nd case). I misinterpreted it as the current that was required but it was the peak current that could be provided by the opamp. So my question is would that cause any physical damage to the opamp other than simply slowling down the charging of the capacitor? Commented Jan 28, 2021 at 21:24
• The data sheet should have some information about this. If there’s any doubt, there’s half a chance that the diode closest to the opamp can be replaced with an emitter follower. It needs a fast transistor though @paulplusx Commented Jan 28, 2021 at 21:39
• Thanks for your suggestion but before that, I tried something else. First, I reduced the hold capacitance to 4.7nF, and then I added a small 50-ohm resistor in series through which the capacitor would charge. Although the capacitor charges a bit slower now, it still finishes charging right around the middle of the input pulse, so that seems fine to me. So now the peak current is reduced to 50mA which is well within the opamp output spec. What do you think about this approach? Commented Jan 29, 2021 at 0:03
• Did you try it on the maximum sized signal? Leave reply, cause I’m off to bed lol. Commented Jan 29, 2021 at 0:41
• Yes, it's probably a sensible approach if you can live with the slight increase in capacitor charge time. Commented Jan 29, 2021 at 14:29