I’m trying to develop an application where I use an STM32F405RGT6 microcontroller IC to drive a radar that operates in multiple ISM bands (433.92 MHz, 915 MHz, 2.4 GHz, and 5.8 GHz).

The overall idea is to generate a waveform that I want to send using Python-based or MATLAB-based tools, then send it to the SRM32 via a USB connection, get the STM32’s inbuilt DACs (one DAC for I signal, other for Q signal) to send the I and Q signals to an LTC5588-1 IQ modulator chip (LO signal provided by TI2572 frequency synthesizer).

Then the reflected signal will be picked up and demodulated by either an ADL5380 or LTC5586, which sends the baseband waveforms to the STM32’s ADCs (again, 2 ADCs, one for I and the other for Q).

The thing is, the STM32F405RGT6 only has two DMA controllers. Since I want to be transmitting and receiving at the same time (my radar targets are going to be within a few meters), are these two DMA controllers enough?

I was originally thinking that I assign one DMA to transmit and the other to receive, but apparently each DMA can only handle one peripheral at a time. What is a workaround if you know any?

  • \$\begingroup\$ Each DMA controller has many DMA channels. The DAC also should work with a single DMA channel. Have you read the manual how they work, or do you have a specific question? \$\endgroup\$
    – Justme
    May 16, 2021 at 9:32
  • \$\begingroup\$ I read the reference manual, but from what I gather, although the DMA has multiple channels, it can only transfer data from one channel at a time. So if I assigned the receiver Q signal to one channel and the I signal to another, then both of those streams will not be faithfully transferred to memory, right? Only one of those streams will be transferred to memory? \$\endgroup\$ May 16, 2021 at 11:44
  • \$\begingroup\$ Are referring now to sampling with ADC? The ADC ca. only convert a single channel at one given time so if you need to sample simultaneously you need to use two ADCs. And yes only one device may use the memory at one given time as the memory has one bus. So obviously multiple DMA transfers cannot happen on the same bus cycle but they could happen on multiple concecutive bus cycles. \$\endgroup\$
    – Justme
    May 16, 2021 at 11:50
  • \$\begingroup\$ Ah yep, I guess in the comment I ended up referring to the ADC, but the point stands for the other direction too (DAC). It comes down to this - 4 peripherals in total need to be operating simultaneously - two DACs that send out the I and Q signals, and two ADCs that sample the I and Q signals. As you said, since the only one channel of one DMA controller can access the bus at any one time, so wouldn't the other peripherals be stuck unable to transfer data (either to the modulators for the DACs or from the demodulators for the ADCs)? So can I have a system which continuously sends AND receives? \$\endgroup\$ May 16, 2021 at 12:12
  • \$\begingroup\$ Both DMA must access one bus matrix and this bus can surve only one thig at a time, then it is impossible for both DMA to transfer at exactly same time, doesn't it? \$\endgroup\$ Oct 1, 2022 at 9:42

1 Answer 1


Single DMA would be enough if sampling frequency is much lower than DMA/Peripheral bus frequency.

ADC peripheral samples signal and puts digital value to data register. DMA copies this ADC register to destination array before this register is being overwritten by next sample. If DMA bus speed is higher than peripheral register update rate, it can serve several peripheral registers in a queue. Each peripheral uses it's own clock and works with input/output data registers, so DMA queue mechanism do not introduce any signal "stretching" over time.

If DAC and ADC sampling frequencies are relatively high, two DMAs may be used to prevent DMA overrun/underrun. For example, DMA1 for ADC 4MHz; DMA2 for DAC 1MHz, MEMTOMEM, USART. ADC triggered by TIM4, DAC triggered by TIM8, TIM8 triggered by TIM4. When your firmware starts, DMA configured to use circular mode. ADC,DAC and TIM8 peripherals are enabled first, then TIM4 enabled allowing simultaneous start of both DAC and ADC. MEMTOMEM may be used to efficiently copy data from HAL_ADC_ConvHalfCpltCallback and HAL_ADC_ConvCpltCallback to safe memory buffer. In this example ADC/DAC interrupts will take around 5% of time, leaving 95% of time to perform signal processing on safe memory buffer in the main loop.


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