If the ICs are close enough the input capacitors for the second stage converters COULD be combined with the output capacitor of the 1st stage converter.
However, I'd be cautious about using a minimum value capacitor here as there is the potential for dynamic interaction between the various converters - especially so with 3 combined if all are smps. I assume that the 6V/5V regulator is linear as efficiency is then 5/6 = 83%. You can get somewhat more than that with a smps with care but to get much over 90% you'd want a synchronous converter and a limited range of loads.
At a minimum I'd suggest that, if a common capacitor was used, the value should be a minimum of the sum of the values required by the 3 individual designs - and then increase as much as possible above that.
Some regulators may require ESRs in a specified range - with lower and upper limits. You may have to look at the conceptual pole zero diagram which drives this specification and see if you can discern any likely effect from inter regulator interactions. OR, more easily, use a largish cap that does not violate any of the spec sheet values and see how it goes :-).