If a N-MOS gate and P-MOS gate are tied together do you need a pullup or pulldown?

Question

I'm working on MOSEFT logic and I've come across this inverter which uses an N-MOS and a P-MOS.

In case it matters one intended use of this is for very low current indicators and the other is in a 6A circuit that is 8bit PWM driven.

The function is clear to me but often I find that discrete components are left out of simple concept diagrams. Which leads to my questions.

1. Every circuit I've made with MOSFETs so far has had either a pullup or pulldown resistor to hold the gate. Is anything like that needed here?
   

2. If not, then what holds the gates?

3. Does this circuit depend on Vin being specifically high or low? What would happen if it was disconnected or at high-z?
   
   
   

4. Also, is Cout a decoupling capacitor?

Answer 1

Usually there is no pullup or pulldown resistor at the input of an inverter like this, because some other logic gate or circuit is always actively driving it.

We do depend on the input being either close to the power supply voltage (a logic 1) or close to ground (a logic 0). We do not allow such inputs to float or be disconnected, except perhaps for a very short period of time (nanoseconds).

The capacitor at the output is not a decoupling capacitor; it represents the load seen by the inverter's output. The inverter output will be connected to the gates of other MOSFET transistors in other logic gates, and the gate of an MOS transistor is electrically like a capacitor. So, usually we just us a lumped capacitor to represent the expected load.