What are best practices for QFN footprint design for manufacturability?

Question

I've never previously designed a board for mass production (as opposed to boards I hand-solder myself with a soldering iron and rare application of a hot-air station), but it's looking like I'm going to need to quite soon. Most things I can figure out myself, but I'm having a hard time finding information on how to design footprints for QFN packages (particularly whether the recommendations for very large QFNs also apply to small QFNs like those used by the LT8336 and LT8618C, both of which are used on my board).

Many of the resources I can find say that using paste over the entire thermal pad is too much solder, and will raise the part off the board enough to prevent the pins from reflowing properly. But is this true of all QFN devices, or would this not matter as much for the tiny ones where the thermal pad isn't that much bigger than the pins?

Also, what's the best way to place the thermal vias? I don't want to put too many thermal vias that all the solder wicks away instead of forming a bond between the pad and the device, but I don't have the budget to use plugged vias. LT doesn't provide any recommendations on this, unfortunately.

They also don't say anything about whether I should be using solder-mask defined or non-solder-mask defined pads, which I know can be important for fine-pitch SMD components, but I don't understand why. Is that important in this case, or is that not until you get to the ultra-fine pitch BGAs that you need to worry about that?

In short: PCBs and PCB assembly are expensive, how do I make sure it works right first time with QFNs? I have enough worries about whether the design itself will work adequately, I'd like to not have to worry about whether the parts will even solder properly.

Answer 1

Many of the resources I can find say that using paste over the entire thermal pad is too much solder, and will raise the part off the board enough to prevent the pins from reflowing properly. But is this true of all QFN devices, or would this not matter as much for the tiny ones where the thermal pad isn't that much bigger than the pins?

Yes, paste mask over the entire thermal pad is most likely too much.

But I wouldn't worry too much about it. Your assembler will modify your stencil data according to their process knowledge. Good stencil design is almost an art of its own.

I personally worry at least a little about stencil design, because I order boards and stencils for quick prototyping from pooling and/or cheap Chinese fabricators occasionally. Those shops will most likely manufacture your stencil 1:1 to your stencil data. So for thermal pads I have only 50% coverage and make my lands rounded rectangles so the openings in the stencil become rounded rectangles as well (so the paste doesn't stick to the corners when lifting the stencil).

For mass production: Let the assembler worry about it.

Also, what's the best way to place the thermal vias? I don't want to put too many thermal vias that all the solder wicks away instead of forming a bond between the pad and the device, but I don't have the budget to use plugged vias.

Having any number of open vias in your thermal pad is probably not a good idea. If you can't afford filled vias you can prevent solder from flowing into the vias by using fancy stencil and solder mask design. You should talk to your assembler about this. A decent and experienced assembler might already have a solution for your problems and can give you design advice.

They also don't say anything about whether I should be using solder-mask defined or non-solder-mask defined pads, which I know can be important for fine-pitch SMD components, but I don't understand why. Is that important in this case, or is that not until you get to the ultra-fine pitch BGAs that you need to worry about that?

I never worried about solder mask defined pads for QFNs. As you said: That becomes a thing with BGAs.

As for the footprint itself the datasheet recommendations of reputable manufacturers are usually a good starting point. You can also use footprint calculators that take IPC recommendations into account. There are third party tools for this or your CAD tool might even have such a calculator integrated.

But again: It's always a good idea to ask your assembler. They might give you a recommendation that worked fine thousands and thousands of times. Or they might say something like "We never had any issues with the manufacturer's recommendation. Go for it!".

Answer 2

Follow the manufacturer "SUGGESTED PCB LAYOUT". For the LT8336 is on page 22, for the LT8618C is on page 25 of their datasheet. If the openings for the pads are too large the stencil manufacturer may give you the option to add an "X" or "+" in the opening. I would not worry too much about it. For first runs of new boards you don't (ever) make large quantities to iron out any design errors. You may not be aware of what the stencil looks like if you are contracting the assembly. It will be part of the NRE (Non-Recurring Engineering) charge. There are more important things to worry about, the actual electrical/mechanical design, than a QFN pad.