Why we need clock pulse in sequential circuits?

Question

I need to know why do we need clock pulse in sequential circuits but not in combinational circuits?

Answer 1

First of all, not all sequential circuits (circuits with feedback) have clocks.

However, the design of asynchronous state machines is very esoteric, requiring the consideration of all possible glitch and race paths through the logic in order to get it right, and I suspect that it is not generally taught these days.

Therefore, simple asynchronous state machines are encapsulated in the form of standard types of clocked flip-flops (T, D, S-R, J-K, etc.) and all higher-order circuits are built using clocked techniques, which vastly simplifies their design. It also vastly simplifies the design of software tools that can synthesize such circuits.

Answer 2

Since sequential circuits have feedback, running them with no delay would produce little useful result as they would basically just oscillate. A clock source is used to control what actions should be taken at a specific time.

I recommend you design (and build) some of both types and the need for a clock will quickly become evident.

Answer 3

Combinational circuits have outputs that depend on inputs. They do not have mechanisms that changing the mapping of input to output - inputs always map to outputs in a consistent way.

Sequential circuits also have outputs that depend on inputs BUT the outputs also depend on the "state" that the sequential circuit is currently adopting. A change from state n to state n+1 can remap how the outputs depend on the inputs. The change of state is brought about by a clock pulse.

Answer 4

If a circuit has some inputs and outputs, and if the elements within the circuit can be ranked such that level 0 elements depend only upon the circuit's inputs, and the elements of each higher level depend only upon the circuit's inputs or lower-level elements, then the circuit is said to be combinatorial. If the inputs assume a certain state, then it may take awhile for everything to react to them, but after some period of time the outputs will assume a state which depends entirely upon the inputs. No circuit element will change state unless or until some of the inputs do so. Such a circuit is called "purely combinatorial".

If a circuit contains any feedback paths, such a circuit is not combinatorial but instead "sequential". In general, the behavior of sequential circuits will vary depending upon the order in which various events occur. If a circuit consists of nothing but registers (flip flops) which all share a common clock, whose data inputs are driven by purely-combinatorial logic fed by the output of themselves and each other, then there will be a short time after each clock pulse where data may propagate through the combinatorial logic; once that time has elapsed, nothing at all will happen until the next clock pulse. If the time between clock pulses is exceeds the worst-case time for everything (including the input circuitry of the flip flops) to settle out, the order in which events occur will depend only upon the number of clock pulses required to produce them, and not upon the speed of any combinatorial circuitry. All this allows for very easy timing analysis: figure out the worst-case propagation times, and confirm that they're shorter than the space between clock pulses. If so, timings may be determined by "counting" clock pulses.

If a circuit contains feedback paths which do not involve shared-clock registers, then it is likely that the sequence in which important events occur will depend upon the exact delays imposed by combinatorial elements. Such dependencies are called "race conditions" [two events go through different logic paths, and there's a "race" to see which one gets output first]. It is in general much easier to say e.g. that a change to combinatorial circuit's input will propagate to its output in something under 10ns, than to say that such propagation will take between 8ns and 12ns. While it is possible to construct sequential circuits that do not require clocks, such circuits invariably involve many race conditions, and designing things so that the correct events will win every race is in general quite difficult. Use of clocked logic makes it much easier to ensure that every race is won by the correct event (it even allows one to deliberately engineer in "ties", where two events are deemed to have happened simultaneously).