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Seeking help with the following datasheet. Section 9.4.3

enter image description here

Didn't understand the above calculations. It states that for inductive load energy dissipation, the energy from the source and the load is dumped onto the high-side switch equivalent to EHSD.

E = P * t = V* I *t makes sense.

I couldn't grasp the further steps. They defined Tdecay. VDS is a constant here, so, out of integration. How do we get at the end result?

enter image description here

Corresponding to the same VDS, Clamp is implemented so that the FET doesn't break down by negative voltage. With the above diagram how exactly is the clamping happening i.e. after it hits 0V, then it pulls up to reach to VDS, Clamp?

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Although energy is power * time as you have stated, your equation E = V * I * T fails to take into account that the current is decaying after each switch "off" of the MOSFET. Looking at the figure 9.12 that you have included in your question, you are integrating the product of V * I from time 0 to T(decay), which is the blue section of the chart. At each point on the Iout curve is multiplied by Vout, and so the area under the resulting curve would be less than Vout * peak Iout.

The energy stored in an inductor at a given instant is equal to 1/2LI2, so all of this energy must be dissipated somewhere. Looking at the figure below from the same data sheet, you can see that when the FET is turned off, the voltage on the output (Vout) would become a large negative value. However, the gate voltage is clamped to the power supply, so it cannot follow. Once the output voltage (FET source) is sufficiently less than the gate voltage, the FET will turn on, conducting so that the current decay occurs with power dissipated in the FET (and in coil resistance R). When the inductor is discharged, the voltage Vout rises back up to ground, and the gate-to-source voltage returns to zero, turning off the FET.

enter image description here

The drain voltage in the schematic above is labeled Vs, which is a little confusing. For the sake of argument, let's say you were running with Vs as 24 volts, the zener voltage was 35 volts, and the gate-source threshold voltage is 5 volts. When you are switching an inductive load, current is flowing from Vout to ground, and when you shut off the FET, Vout spikes strongly negative. But Vout is the FET source, and zener won't let the gate go below negative 11 volts (24-35). So When Vout gets to negative 16 volts (-11-5), the gate-source voltage is 5 volts and the FET turns on, providing the inductance with current until its voltage rises back up above -11 volts, at which time the FET is off again. So after turn-off the FET only conducts when the voltage is negative, during Tdecay.

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  • \$\begingroup\$ I kinda understand, should i take the expressions as a 'fact' & not worry to much about it? \$\endgroup\$
    – Harkirat
    Commented Apr 22, 2023 at 15:06
  • \$\begingroup\$ How does the clamp voltage V(DS, Clamp) work during t(decay)? Just a bit confused about this part. The Gate doesn't follow the large negative voltage at the Source(OUT Pin) due to the fact that it(Gate) is shifted to +V(S)? \$\endgroup\$
    – Harkirat
    Commented Apr 22, 2023 at 15:26
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    \$\begingroup\$ Got too long-winded so I edited the answer. \$\endgroup\$ Commented Apr 23, 2023 at 19:36
  • \$\begingroup\$ Really appreciate the help. I presume "providing the inductance with current until its voltage rises back up above 11 volts" meant like the V(out) coming back up to 0V? \$\endgroup\$
    – Harkirat
    Commented Apr 24, 2023 at 14:18
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    \$\begingroup\$ I meant -11 volts, so I edited again. \$\endgroup\$ Commented Apr 24, 2023 at 18:09

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