I want to draw something to indicate the response time of a power supply to a change on the load side. Here is what I came up with and I want to ask if it is the correct interpretation:
Does the voltage drop happen exactly at the time that the current draw is being increased?
Yes, but capacitance and inductance can make slight delays from the source to the load. In most power systems they are probably in the ms range, but don't have to be.
Should the time that current reaches it peak be in sync with the time the voltage is also retuned to normal?
Again there will be some delay if there is a lot of inductance.
Well, no idea, you don't describe your system at all -- but there are a few typical cases, and one might argue anything else is pathological and would indicate bad design of the system, anyway.
simulate this circuit – Schematic created using CircuitLab
When one says "load step", they mean step: an ideal step change in current. Actual-ideal-slope is impossible, and some bandwidth is implied. For supply testing, that will generally be a bandwidth in excess of the supply's. So, for most purposes, a few µs is good enough.
For voltage, you might show a bounded range within which the output is expected to settle; if your system is better constrained, a narrower range can be offered, or even just a typical (actual measured) response.
Whether it has a limited slope (mustard), a sharp lead-in (teal), or oscillation (gold), depends on characteristic. All of these are typical, depending on type of power supply (linear/switching, CC/CV/various) and output filter network (or if applicable). Note that, while I use a linear RLC model to represent it here, there is the (generally nonlinear) control loop which may itself manifest as some source inductance and resistance. Not just the filter components per se.
The rising slope is typically the more interesting case, as overshoot is dictated by control response, and settling is dominated by idle load (output C discharging slowly) until it comes back into regulation. This can be alleviated by testing with some base load (e.g. stepping from 50 to 100% rated, and back), or provided as information to show how your system responds under diverse load conditions (e.g. step from 1 to 50%, 1 to 100%, etc.).
The voltage should probably be read with a modest bandwidth, to filter out lead inductance (sudden much sharper descent: notice I only showed the R||L case; the R+L case has unlimited response for a current step approaching infinity) and switching ripple. You might also average multiple trials together to reduce uncorrelated noise (i.e. switching ripple).
