Search Results
| Search type | Search syntax |
|---|---|
| Tags | [tag] |
| Exact | "words here" |
| Author |
user:1234 user:me (yours) |
| Score |
score:3 (3+) score:0 (none) |
| Answers |
answers:3 (3+) answers:0 (none) isaccepted:yes hasaccepted:no inquestion:1234 |
| Views | views:250 |
| Code | code:"if (foo != bar)" |
| Sections |
title:apples body:"apples oranges" |
| URL | url:"*.example.com" |
| Saves | in:saves |
| Status |
closed:yes duplicate:no migrated:no wiki:no |
| Types |
is:question is:answer |
| Exclude |
-[tag] -apples |
| For more details on advanced search visit our help page | |
Results tagged with fifo
Search options not deleted
user 311028
FIFO (First In, First Out) is one way of managing a buffer for data
0
votes
1
answer
599
views
What are the possible strategies to transfer data from an FPGA accelerator to a hard-core CPU? [closed]
accelerator is an AXI slave that should be programmed and started by the CPU
I need to transfer approximately 240 KB/sec from the FPGA to the CPU
The possibilities I could think of are:
Create a sort of FIFO … Use an external FIFO: use one of VIVADO modules to implement a FIFO between my accelerator and the CPU. I guess this forces me to implement an AXI master interface on my accelerator? …
- 99.9k