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Results tagged with fifo
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user 311028
FIFO (First In, First Out) is one way of managing a buffer for data
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What are the possible strategies to transfer data from an FPGA accelerator to a hard-core CPU? [closed]
accelerator is an AXI slave that should be programmed and started by the CPU
I need to transfer approximately 240 KB/sec from the FPGA to the CPU
The possibilities I could think of are:
Create a sort of FIFO … Use an external FIFO: use one of VIVADO modules to implement a FIFO between my accelerator and the CPU. I guess this forces me to implement an AXI master interface on my accelerator? …
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