For Xilinx's UltraScale and UltraScale+ family, the architecture guide says: "There are 16 storage elements per CLB slice. All can be configured as either edge-triggered D-type flip-flops or level-sensitive latches. The latch option is by top or bottom half of the CLB. If the latch option is selected on a storage element, all eight storage elements in that half must be either used as latches or left unused. When configured as a latch, the latch is transparent when the CLB clock input (CLK) is High." As @JoeHass said: it does not waste resources because registers are reconfigured as latches.