Skip to main content
Electrical Engineering
Ironil's user avatar
Ironil's user avatar
Ironil's user avatar
Ironil
  • Member for 10 years, 1 month
  • Last seen more than 2 years ago
Profile Activity
Stats
73
reputation
6k
reached
3
answers
2
questions
Communities
Badges
View all badges
This user doesn’t have any gold badges yet.
This user doesn’t have any silver badges yet.
8
bronze badges
Top tags
View all tags
4
Score
2
Posts
40
Posts %
2
Score
2
Posts
40
Posts %
2
Score
2
Posts
40
Posts %
2
Score
1
Posts
20
Posts %
2
Score
1
Posts
20
Posts %
0
Score
1
Posts
20
Posts %
Top posts
answer
2
Modeling a Time to Digital Converter in Verilog-AMS
Feb 25, 2016
answer
2
how to understand xilinx RTL schematics
Mar 1, 2016
answer
2
TX/RX pins on Xilinx Zynq
Apr 5, 2016
question
1
Modeling a Time to Digital Converter in Verilog-AMS
Feb 24, 2016
question
0
Measure CMRR of amplifier in a single HSPICE simulation?
Dec 26, 2016
Top network posts
View all network posts
10
Use of curve_fit to fit data
5
Two's complement in verilog