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Captain Barnacles
  • Member for 9 years, 1 month
  • Last seen more than 4 years ago
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7.4v to 3.3v convert
edited body
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PCIe Gen2 PLL lock issue
When I read your post you have need to have a few goes locking the PHY PLL to the clock. Then you power it off and back on and it's again unlocked. So do you need to repeat your process ? Have you got a 100MHz signal generator you can connect into the PHY ? To rule out the PC. The datasheet may also have a sequence for the PLL getting lock.
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Can I connect a heating element to a solar panel to heat a hot tub
This is a really good idea. Use the sun to heat a large thermal mass (the water tank) and then the coil and pump circulating through it back to the hot tub makes a great heat exchanger.
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STM32L1 Discovery Kit 5MHz PWM Generation
A few thoughts, there is a lot of ringing on the signal. Do you know what the max freq that the timer can put out ? Your description sounds like it doesnt have enough bandwidth. Have you got a pull down resistor on the output pin or straight to the scope ?
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Difference between LVDS and "Low Power LVDS"
Yes I see that now having re-read it. I've adjusted the answer accordingly..
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Difference between LVDS and "Low Power LVDS"
Tidied up answer to include the mode in question
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Is the isolation necessary in this circuit?
You are isolated so don't need the opto, unless they are doing level shifting ?
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