Important note: You are not helping me do my homework. This is for a competition for engineering students, that encourages you to "use your network" ;)

I've got this pattern for a frequency divider that divides the clock by 5. It's supposed to have one major problem, but i can't seem to figure out exactly what it is.

https://i.stack.imgur.com/3hMDN

The options I have to fix this problem is:

• X==(000|001|100), Y==(001)
• X==(000|001|010|011), Y==(010|011)
• X==(001|010|011), Y==(000)
• Both a) and c) are correct!

I've taken the time to map out the signals in the original design and in option number 3, as i thought that was the answer.

http://imgur.com/dD30q

I've shifted the clock one half clock cycle, whoops. Shouldn't change anything though. The rest is done by hand.

Does anyone here have any good suggestions?

Important note: You are not helping me do my homework. This is for a competition for engineering students, that encourages you to "use your network" ;)

I've got this pattern for a frequency divider that divides the clock by 5. It's supposed to have one major problem, but I can't seem to figure out exactly what it is.

The options I have to fix this problem is:

• X==(000|001|100), Y==(001)
• X==(000|001|010|011), Y==(010|011)
• X==(001|010|011), Y==(000)
• Both a) and c) are correct!

I've taken the time to map out the signals in the original design and in option number 3, as I thought that was the answer.

I've shifted the clock one half clock cycle, whoops. Shouldn't change anything though. The rest is done by hand.

Does anyone here have any good suggestions?