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module csm51a_proj3_tb(
    );

    reg reset, clk, x1, x0;
    wire z0, z1;

    csm51a_proj3 csm51a_proj3
    (
    .r(reset),
    .x1(x1),
    .x0(x0),
    .clk(clk),
    .z0(z0),
    .z1(z1)
    );
 
    initial begin
    reset=0;x1=1;x0=1;clk=0;
    #10;
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=1;x0=1;clk=0;
    #10
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    reset=1;x1=0;x0=0;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    reset=1;x1=0;x0=0;clk=1;
    #10;
    reset=0;x1=1;x0=1;clk=0;
    #10;
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    reset=1;x1=0;x0=0;clk=1;
    #10;
    end
    
endmodule

    module csm51a_proj3_tb(
    );

    reg reset, clk, x1, x0;
    wire z0, z1;
initial begin clk=0; end
always begin #5 clk=~clk; end
    csm51a_proj3 csm51a_proj3
    (
    .r(reset),
    .x1(x1),
    .x0(x0),
    .clk(clk),
    .z0(z0),
    .z1(z1)
    );
    initial begin
    reset=0;x1=1;x0=1;//clk=1;
    #10;
    reset=0;x1=0;x0=1;//clk=1;
    #10;
    reset=0;x1=1;x0=1;//clk=1;
    #10;
    reset=1;x1=0;x0=0;//clk=1;
    #10;
    reset=0;x1=0;x0=1;//clk=1;
    #10;
    reset=0;x1=0;x0=1;//clk=1;
    #10;
    reset=0;x1=0;x0=1;//clk=1;
    #10;
    reset=0;x1=0;x0=1;//clk=1;
    #10;
    reset=1;x1=0;x0=0;//clk=1;
    #10;
    reset=0;x1=1;x0=1;//clk=1;
    #10;
    reset=1;x1=0;x0=0;//clk=1;
    #10;
    end
    
endmodule

I have everything right now, but the output I desire should be 00 00 11 00 00 00 00 10 00 00 00 not all 00s (z1z0). Can someone tell me what is wrong with my code? I've checked my Kmap numerous times.

The JKFFs I should be implementing is:

    module csm51a_proj3_tb(
    );

    reg reset, clk, x1, x0;
    wire z0, z1;

    csm51a_proj3 csm51a_proj3
    (
    .r(reset),
    .x1(x1),
    .x0(x0),
    .clk(clk),
    .z0(z0),
    .z1(z1)
    );

    initial begin
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    end
    
endmodule

I have everything right now, but the output I desire should be 00 00 11 00 00 00 00 10 00 00 00 when the clock is 1(z1z0). Can someone tell me what is wrong with my code? I've checked my Kmap numerous times.

The JKFFs I should be implementing is:

module csm51a_proj3_tb(
    );

    reg reset, clk, x1, x0;
    wire z0, z1;

    csm51a_proj3 csm51a_proj3
    (
    .r(reset),
    .x1(x1),
    .x0(x0),
    .clk(clk),
    .z0(z0),
    .z1(z1)
    );

    initial begin
    reset=0;x1=1;x0=1;clk=0;
    #10;
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=1;x0=1;clk=0;
    #10
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    reset=1;x1=0;x0=0;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=0;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    reset=1;x1=0;x0=0;clk=1;
    #10;
    reset=0;x1=1;x0=1;clk=0;
    #10;
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    reset=1;x1=0;x0=0;clk=1;
    #10;
    end
    
endmodule

I have everything right now, but I cannot get this to compile, because of z0 and z1 in JKFF (where I assign z1 and z0). It says, "concurrent assignment to a non-net z0 is not permitted." Please help!

The JKFFs I should be implementing is:

module csm51a_proj3(
input r,
input x1,
input x0,
input clk,
output z0,
output z1
);
wire a1;
wire s0,s1,z1, z0; 
jkff i_jkff
( 
.r(r),
.x1(x1),
.x0(x0),
.clk(clk),
.z0(z0),
.z0(z1)
);  
endmodule

module jkff(clk, r, x1, x0, z1, z0);
input clk;
input r;
input x1;
input x0;
output reg z1;
output reg z0;
reg s0, s1;
initial begin s0<=1'b0; s1<=1'b0; end
 wire a1, a2, a3, a4, J1, K1, J0, K0;
 assign z0=(x1&&s0&&!s1);
 assign z1=(s1&&x0&&(!s0||x1));      
 
 assign a1=(x1||s0);
 assign J1=(a1&&x0);
 assign a2=(x1||!s0);
 assign K1=(x0&&a2);
 assign a3=(x1||s1); 
 assign J0=(x0&&!s1);
 assign a4=(x1||s1);
 assign K0=(a4&&x0);

 always @(posedge clk or posedge r)
 begin
    if (r) begin
        s1<=0;
        s0<=0;
        end
    else begin
    case ({J1,K1})
    2'b00: s1<=s1;
    2'b01: s1<=1'b0;
    2'b10: s1<=1'b1;
    2'b11: s1<=~s1;
    endcase
    case ({J0,K0})
    2'b00: s0<=s0;
    2'b01: s0<=1'b0;
    2'b10: s0<=1'b1;
    2'b11: s0<=~s0;
    endcase
end
end
endmodule

module csm51a_proj3_tb(
);

reg reset, clk, x1, x0;
wire z0, z1;

csm51a_proj3 csm51a_proj3
(
.r(reset),
.x1(x1),
.x0(x0),
.clk(clk),
.RN(z0),
.RG(z1)
);

initial begin
reset=0;x1=1;x0=1;clk=1;
#10;
reset=0;x1=0;x0=1;clk=1;
#10;
reset=0;x1=1;x0=1;clk=1;
#10;
reset=1;x1=0;x0=0;clk=1;
#10;
reset=0;x1=0;x0=1;clk=1;
#10;
reset=0;x1=0;x0=1;clk=1;
#10;
reset=0;x1=0;x0=1;clk=1;
#10;
reset=0;x1=0;x0=1;clk=1;
#10;
reset=1;x1=0;x0=0;clk=0;
#10;
reset=0;x1=1;x0=1;clk=1;
#10;
reset=1;x1=0;x0=0;clk=0;
#10;
end
endmodule

I have everything right now, but the output I desire should be 00 00 11 00 00 00 00 10 00 00 00 not all 00s (z1z0). Can someone tell me what is wrong with my code? I've checked my Kmap numerous times.

The JKFFs I should be implementing is:

module csm51a_proj3(
input r,
input x1,
input x0,
input clk,
output z0,
output z1
);

jkff i_jkff
( 
.r(r),
.x1(x1),
.x0(x0),
.clk(clk),
.z0(z0),
.z1(z1)
);  
endmodule

    module jkff(
input clk, r, x1, x0,
output wire z1,z0 
);
reg s0,s1;
initial begin s0<=1'b0; s1<=1'b0; end
assign z0=(x1&&!s0&&s1);
assign z1=(s1&&x0&&(!s0||x1));     
   
wire a1, a2, a3, J1, K1, J0, K0;
assign a1=(x1||s0);
assign J1=(a1&&x0);
assign a2=(x1||!s0);
assign K1=(x0&&a2);
assign a3=(x1||s1); 
assign J0=(x0&&!s1);
assign K0=(a3&&x0);

 always @(posedge clk or posedge r)
 begin
    if (r) begin
        s1<=0;
        s0<=0;
        end
    else begin
    case ({J1,K1})
    2'b00: s1<=s1;
    2'b01: s1<=1'b0;
    2'b10: s1<=1'b1;
    2'b11: s1<=~s1;
    endcase
    case ({J0,K0})
    2'b00: s0<=s0;
    2'b01: s0<=1'b0;
    2'b10: s0<=1'b1;
    2'b11: s0<=~s0;
    endcase
end
end
endmodule

    module csm51a_proj3_tb(
    );

    reg reset, clk, x1, x0;
    wire z0, z1;

    csm51a_proj3 csm51a_proj3
    (
    .r(reset),
    .x1(x1),
    .x0(x0),
    .clk(clk),
    .z0(z0),
    .z1(z1)
    );

    initial begin
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=0;x1=0;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    reset=0;x1=1;x0=1;clk=1;
    #10;
    reset=1;x1=0;x0=0;clk=0;
    #10;
    end
    
endmodule