Skip to main content
5 of 10
added 12 characters in body

Finite State Machine, Verilog Code

My code compiles now, but my outputs RG (z1) and RN (z0) are incorrect and show up as X's in the simulation. I have no idea how to implement double JKFFs using "always @" code. I think I need to somehow fix my jkff module so that I do not get X's in my code.

Simulation Result

The JKFFs I should be implementing is: JKFFs

module main_file(
input r,
input x1,
input x0,
input clk,
output RN,
output RG
);
wire ss0, ss1, a1; 
jkff i_jkff
( 
.s0(ss0),  
.s1(ss1)
);  
assign a1=(!ss0||x1);
assign RN=(x0&&ss1&&a1);
assign RG=(x1&&ss1&&!ss0);
endmodule

Below is the jkff implementation:

module jkff(
input clk, r, x1, x0,
output reg s0,
output reg s1
);
 wire a1, a2, a3, a4, J1, K1, J0, K0;
 assign a1=(x1||s0);
 assign J1=(a1&&x0);
 assign a2=(x1||!s0);
 assign K1=(x0&&a2);
 assign a3=(x1||x0);
 assign J0=(a3&&!s1);
 assign a4=(x1||s1);
 assign K0=(a4&&x0);
 
 always @(posedge clk or posedge r)
 begin
    if (r) begin
        s1<=0;
        end
    else begin
    case ({J1,K1})
    2'b00: s1<=s1;
    2'b01: s1<=1'b0;
    2'b10: s1<=1'b1;
    2'b11: s1<=~s1;
    endcase
end
end
endmodule

Below is the test bench

module main_file_tb(
);

reg a;
reg b;
reg c;
reg d;
wire e;
wire f;

main_file main_file
(
.r(a),
.x1(b),
.x0(c),
.clk(d),
.RN(e),
.RG(f)
);

initial begin
a=0;b=1;c=1;d=1;
#10;
a=0;b=0;c=1;d=1;
#10;
a=0;b=1;c=1;d=1;
#10;
a=1;b=0;c=0;d=0;
#10;
a=0;b=0;c=1;d=1;
#10;
a=0;b=0;c=1;d=1;
#10;
a=0;b=0;c=1;d=1;
#10;
a=0;b=0;c=1;d=1;
#10;
a=1;b=0;c=0;d=0;
#10;
a=0;b=1;c=1;d=1;
#10;
a=1;b=0;c=0;d=0;
#10;
end
endmodule