Timeline for Why is D flip-flop positive edge triggered instead of level triggered?
Current License: CC BY-SA 4.0
11 events
| when toggle format | what | by | license | comment | |
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| Aug 25, 2021 at 14:26 | history | edited | JRE | CC BY-SA 4.0 |
deleted 19 characters in body; edited title
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| Aug 25, 2021 at 14:22 | answer | added | Antonio51 | timeline score: 0 | |
| Dec 30, 2015 at 15:57 | history | tweeted | twitter.com/StackElectronix/status/682228976954249216 | ||
| Dec 13, 2015 at 3:44 | vote | accept | Victor Lin | ||
| Dec 13, 2015 at 3:41 | vote | accept | Victor Lin | ||
| Dec 13, 2015 at 3:43 | |||||
| Dec 12, 2015 at 18:54 | answer | added | Martin Zabel | timeline score: 5 | |
| Dec 12, 2015 at 18:47 | comment | added | Bimpelrekkie | No it is not, it keeps the state it was in at the moment that the clock became 1 (as it is supposed to). Note that NAND1 and NOT1 form a memory and so do NAND3 and 4. When S = 1 R must be 0 so NAND4 will ignore D. When R = 1 NAND3 and 4 cannot change state as as S = 0. R and S cannot be both 1 at the same time. | |
| Dec 12, 2015 at 17:20 | comment | added | Victor Lin | Thanks for the reply, i've read the link you provided, but it doesn't really answer my question, it just explains why edge trigger is more precise. After reading it, I still don't understand how this DFF is considered edge triggered, since edge trigger would be the output values can only be affected when the clock is on an edge; but from my understanding, this DFF output is affected whenever the clock is on the level 1 | |
| Dec 12, 2015 at 17:10 | comment | added | user34299 | It is a good question. I found this Why edge triggering is preferred over level triggering? | |
| Dec 12, 2015 at 16:49 | review | First posts | |||
| Dec 13, 2015 at 1:55 | |||||
| Dec 12, 2015 at 16:46 | history | asked | Victor Lin | CC BY-SA 3.0 |