Why is D flip-flop positive edge triggered instead of level triggered?

Question

I'm trying to understand this D type positive edge flip-flop:

^{simulate this circuit – Schematic created using CircuitLab}

I'm having problem understanding why it is positive edge triggered and not level triggered.

I understand that when the clock is 0, NAND 2 and 3 will both output 1 locking the current values of the SR latch on the right.

When the clock value is 1, it stops affecting the circuit so it can be simplified into something like:

^{simulate this circuit}

Where the circuit will start to be affected by the input of D according to the previous state of the circuit.

If this is how this D type flip flop works, wouldn't it be a level triggered flip flop instead? The input D will affect the set and reset values of the SR latch on the right as long as the clock is 1.

Can someone explain where I've gone wrong in my understanding?

Answer 1

No, your circuit is still a edge-triggered circuit. The pairs NAND1+NAND2 and NAND3+NAND4 lock the state of D when the clock rises from to low to high. Changing D when the clock is high (after the rising edge) does not affect the output.

Let's start with Clk = 0, then is S=1 and R=1.

Now let D=0 during the rising edge of the clock:

• The output of NAND4 will be high.
• The output of NAND3 will be low, because S is still high, thus R=0 => Q=0.
• The output of NAND1 is low.
• The output of NAND2 is high, thus S is high, and R keeps low.

The output of NAND4 will be kept high until the clock is low again because the input connected to R is low regardless of any change on D (after the rising edge).

Please note that the functionality of this circuit relies on the propagation delay of the gates.

Answer 2

If the circuit is a 7474 D - Edge triggered, unless I am wrong, you are not really "wrong".

From the datasheet https://www.ti.com/lit/ds/symlink/sn54ls74a-sp.pdf?ts=1629843026340&ref_url=https%253A%252F%252Fwww.google.it%252F

See the description

For proving this, one must use a "variable slew-rate" clock.

EDIT: to prove that it is really the transition 0 to 1 of the clock that is meaningful, I will add the excitation kmap of the first two RS latches. The behavior of the last (at right) is straightforward. Here is the circuit with feedbacks removed. Kmap coming soon ...

For each change of the input values of (clk, D), follow the values in the map.
Remember that in this map, one only can move horizontally (under change of clk or D, only one at one time), then move vertically until a stable combination is found ... if any ...).
The "state" in the "box" show to what "line" we are heading (shown at the left of the table) ... Continue until we are in a RED case, which is "stable" combination if any.