Suppose we have a type-I PLL whose block diagram is shown below:
Here \$k_{pd}\$ is the average gain of the phase detector producing the control voltage \$V_c\$ which is input to the Voltage Controlled oscillator (VCO). In the feedback path we have a frequency divider which divides its input frequency by N.
Suppose input frequency is given by \$\omega_{ref} (=2\pi*f_{ref})\$ and output frequency is \$\omega_{out}\$, then in general the phase difference between the input and the outputfed-back frequency is given by: \$(\omega_{ref} - \omega_{out}/N)t + \Phi_{ref} - \Phi_{out}/N\$.TheThis error signal is input to the phase detector. The steady state phase difference should be given by: \$\Phi_{ref} - \Phi_{out}\$ with \$\omega_{ref} = \omega_{out}/N\$. Does, this frequency relationship hold true even if \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$, which is beyond the range where the PLL will get locked?
In other words, does the frequency relationship between input and output (\$\omega_{ref} = \omega_{out}/N\$) maintained even if the PLL doesn't get locked? If not, what happens to the output signal (in steady state) if PLL is beyond the lock range (given by \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$)?
Suppose we have a type-I PLL whose block diagram is shown below:
Here \$k_{pd}\$ is the average gain of the phase detector producing the control voltage \$V_c\$ which is input to the Voltage Controlled oscillator (VCO). In the feedback path we have a frequency divider which divides its input frequency by N.
Suppose input frequency is given by \$\omega_{ref} (=2\pi*f_{ref})\$ and output frequency is \$\omega_{out}\$, then in general the phase difference between the input and the output is given by: \$(\omega_{ref} - \omega_{out}/N)t + \Phi_{ref} - \Phi_{out}/N\$.The steady state phase difference should be given by: \$\Phi_{ref} - \Phi_{out}\$ with \$\omega_{ref} = \omega_{out}/N\$. Does, this hold true even if \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$, which is beyond the range where the PLL will get locked?
In other words, does the frequency relationship between input and output (\$\omega_{ref} = \omega_{out}/N\$) maintained even if the PLL doesn't get locked? If not, what happens to the output signal (in steady state) if PLL is beyond the lock range (given by \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$)?
Suppose we have a type-I PLL whose block diagram is shown below:
Here \$k_{pd}\$ is the average gain of the phase detector producing the control voltage \$V_c\$ which is input to the Voltage Controlled oscillator (VCO). In the feedback path we have a frequency divider which divides its input frequency by N.
Suppose input frequency is given by \$\omega_{ref} (=2\pi*f_{ref})\$ and output frequency is \$\omega_{out}\$, then in general the phase difference between the input and the fed-back frequency is given by: \$(\omega_{ref} - \omega_{out}/N)t + \Phi_{ref} - \Phi_{out}/N\$.This error signal is input to the phase detector. The steady state phase difference should be given by: \$\Phi_{ref} - \Phi_{out}\$ with \$\omega_{ref} = \omega_{out}/N\$. Does, this frequency relationship hold true even if \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$, which is beyond the range where the PLL will get locked?
In other words, does the frequency relationship between input and output (\$\omega_{ref} = \omega_{out}/N\$) maintained even if the PLL doesn't get locked? If not, what happens to the output signal (in steady state) if PLL is beyond the lock range (given by \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$)?
Confusion: Lock range of PLL
Suppose we have a type-I PLL whose block diagram is shown below:
Here \$k_{pd}\$ is the average gain of the phase detector producing the control voltage \$V_c\$ which is input to the Voltage Controlled oscillator (VCO). In the feedback path we have a frequency divider which divides its input frequency by N.
Suppose input frequency is given by \$\omega_{ref} (=2\pi*f_{ref})\$ and output frequency is \$\omega_{out}\$, then in general the phase difference between the input and the output is given by: \$(\omega_{ref} - \omega_{out}/N)t + \Phi_{ref} - \Phi_{out}/N\$.The steady state phase difference should be given by: \$\Phi_{ref} - \Phi_{out}\$ with \$\omega_{ref} = \omega_{out}/N\$. Does, this hold true even if \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$, which is beyond the range where the PLL will get locked?
In other words, does the frequency relationship between input and output (\$\omega_{ref} = \omega_{out}/N\$) maintained even if the PLL doesn't get locked? If not, what happens to the output signal (in steady state) if PLL is beyond the lock range (given by \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$)?