Timeline for Different ways of using DSP slices in Spartan 6 FPGA
Current License: CC BY-SA 3.0
9 events
| when toggle format | what | by | license | comment | |
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| Nov 1, 2019 at 20:34 | comment | added | DKNguyen | @JonRB That would be method 2, using the Core generator. | |
| Apr 13, 2017 at 12:32 | history | edited | CommunityBot |
replaced http://electronics.stackexchange.com/ with https://electronics.stackexchange.com/
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| Feb 5, 2017 at 12:02 | comment | added | user16222 | shouldn't it be in the xilinx ide template? That is the usual place you instantiate a function provided at silicon (ram, pll etc..) | |
| Feb 5, 2017 at 8:31 | answer | added | Bert Sierra | timeline score: 1 | |
| Aug 28, 2016 at 18:28 | history | edited | Marcus Müller | CC BY-SA 3.0 |
deleted 5 characters in body
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| Aug 28, 2016 at 18:21 | answer | added | FusterCluck | timeline score: 1 | |
| Mar 12, 2016 at 18:09 | answer | added | Martin Zabel | timeline score: 1 | |
| Mar 6, 2016 at 5:12 | answer | added | alex.forencich | timeline score: 3 | |
| Mar 6, 2016 at 3:26 | history | asked | ironstein | CC BY-SA 3.0 |