Maybe it is really easy question but I spent two hours looking for solution and information in the internet and still I can't push it to work.

I need to do arithmetic left shit operation. I used standard SLA operator.

ModelSim during compilation shows an error:

Blockquote ** Error: (vcom-1581) No feasible entries for infix operator 'sla'. ** Error: Bad right hand side (infix expression) in variable assignment.

My code

constant Vlsb : std_logic_vector(47 downto 0) := x"00002710CB29";
i_data      : in std_logic_vector(15 downto 0);

.

process(i_clk) is 
    variable data : std_logic_vector(47 downto 0);
begin 
    if(i_rst_asyn = '0') then
        data := (others => '0');
    else
        if(rising_edge(i_clk)) then
            if(i_rst_syn = '1') then
                data := (others => '0');
            else
                data(15 downto 0) := i_data;
                data := data sla 31; -- ERROR LINE
                data := std_logic_vector(signed(data) / signed(Vlsb));              
            end if;
        end if;
    end if; 
    o_data <= data;
end process;

Could sombody tell me what I am doing wrong, please.

Add- I am using std_logic_1164 and numeric_std library in this module.

Maybe it is really easy question but I spent two hours looking for solution and information in the internet and still I can't push it to work.

I need to do arithmetic left shift operation. I used standard SLA operator.

ModelSim during compilation shows an error:

Blockquote ** Error: (vcom-1581) No feasible entries for infix operator 'sla'. ** Error: Bad right hand side (infix expression) in variable assignment.

My code

constant Vlsb : std_logic_vector(47 downto 0) := x"00002710CB29";
i_data      : in std_logic_vector(15 downto 0);

.

process(i_clk) is 
    variable data : std_logic_vector(47 downto 0);
begin 
    if(i_rst_asyn = '0') then
        data := (others => '0');
    else
        if(rising_edge(i_clk)) then
            if(i_rst_syn = '1') then
                data := (others => '0');
            else
                data(15 downto 0) := i_data;
                data := data sla 31; -- ERROR LINE
                data := std_logic_vector(signed(data) / signed(Vlsb));              
            end if;
        end if;
    end if; 
    o_data <= data;
end process;

Could sombody tell me what I am doing wrong, please.

Add- I am using std_logic_1164 and numeric_std library in this module.