Timeline for Taking output from FIFO implemented in verilog

7 events

when toggle format	what		by	license	comment
Jan 21, 2013 at 14:02	answer	added	shuckc		timeline score: 0
Jan 17, 2013 at 11:59	answer	added	Tomas D.		timeline score: 2
Jan 17, 2013 at 10:42	comment	added	andrsmllr		Does 'expecting all 23 rows in single clock' mean that you must have exactly 23 valid data units or can there be less? Is the data b/w FIFO and Consumer pushed by the FIFO, or pulled/requested by the Consumer? If no other module is connected to the FIFO you could replace it by a shift register or put the shift register as a intermediate module b/w FIFO and consumer(as pjc50 proposed).
Jan 17, 2013 at 10:32	comment	added	pjc50		You could empty the fifo into a 23x6 array, one row at a time, and then copy it across to the consumer - is that satisfactory? If extra data arrives in the FIFO in the meantime it won't be included.
Jan 17, 2013 at 10:18	comment	added	gpuguy		@pjc50 But I am allowed to put an additional block between source and consumer. The source and consumer may work asynchronously.
Jan 17, 2013 at 10:14	comment	added	pjc50		If you can't modify the source, and it doesn't output all its rows somewhere, then there's no possible way of getting the data out of it in one clock cycle?
Jan 17, 2013 at 10:06	history	asked	gpuguy	CC BY-SA 3.0