I'm trying to implement a autocorrelation module into my FPGA. I have been doing some reattach across the internet and there are some complicated and advanced methods that use a Fast Fourier Transform (FFT) to do the autocorrelation. However, all I need is a simple implementation, nothing too fancy. I came across this digital logic site that had shown a diagram as:

Essentially what I got out of this was we chain D-Flip-Flops (DFF) to create a shift register. From there we pull from the shift register or different DFFs and run them into a multiplier with the original \$S_{i}\$, then add the output. So my implementation from a program called digital is this:

Which I believe is the same, however, I am noticing some variations. I added more DFFs because I want to be able to correlate more bits. I also am not really sure if I implemented the "Sums" correctly, I also skipped the fist add from the first multiply for this reason. Some other issues I had include issues from the program. I ultimately used this program because I can take the design and get Verilog code out of it. But when I try to export as Verilog I get the error:

Can anyone help confirm if I'm on the right track with this implementation or if it is correct. It seems like the first adder is having issues but I am also unsure of what the first \$C_{i}\$ would be. In verilog I could just set it to a 0 bit but not sure how to do that in a design.

I'm trying to implement a autocorrelation module into my FPGA. I have been doing some research on the internet and there are some complicated and advanced methods that use a Fast Fourier Transform (FFT) to do the autocorrelation. 

However, all I need is a simple implementation, nothing too fancy. I came across this digital logic site that has this diagram:

Essentially, what I got out of this was that we chain D-flip-flops (DFF) to create a shift register. From there we pull from the shift register or different DFFs and run them into a multiplier with the original S_i, then add the output. So my implementation from a program called digital is this:

Which I believe is the same, however, I am noticing some variations. I added more DFFs because I want to be able to correlate more bits. I also am not really sure if I implemented the "Sums" correctly; I also skipped the fist add from the first multiply for this reason. 

Some other issues I had include issues from the program. I ultimately used this program because I can take the design and get Verilog code out of it. But when I try to export as Verilog I get the error:

Can anyone help confirm if I'm on the right track with this implementation or if it is correct? It seems like the first adder is having issues but I am also unsure of what the first C_i would be. In Verilog I could just set it to a 0 bit, but I am not sure how to do that in a design.

I'm trying to implement a autocorrelation module into my FPGA. I have been doing some reattach across the internet and there are some complicated and advanced methods that use a Fast Fourier Transform (FFT) to do the autocorrelation. However, all I need is a simple implementation, nothing too fancy. I came across this digital logic site that had shown a diagram as:

Essentially what I got out of this was we chain D-Flip-Flops (DFF) to create a shift register. From there we pull from the shift register or different DFFs and run them into a multiplier with the original \$S_{i}\$, then add the output. So my implementation from a program called digital is this:

Which I believe is the same, however, I am noticing some variations. I added more DFFs because I want to be able to correlate more bits. I also am not really sure if I implemented the "Sums" correctly, I also skipped the fist add from the first multiply for this reason. Some other issues I had include issues from the program. I ultimately used this program because I can take the design and get verilog code out of it. But when I try to export as verilog I get the error:

Can anyone help confirm if I'm on the right track with this implementation or if it is correct. It seems like the first adder is having issues but I am also unsure of what the first \$C_{i}\$ would be. In verilog I could just set it to a 0 bit but not sure how to do that in a design.

I'm trying to implement a autocorrelation module into my FPGA. I have been doing some reattach across the internet and there are some complicated and advanced methods that use a Fast Fourier Transform (FFT) to do the autocorrelation. However, all I need is a simple implementation, nothing too fancy. I came across this digital logic site that had shown a diagram as:

Essentially what I got out of this was we chain D-Flip-Flops (DFF) to create a shift register. From there we pull from the shift register or different DFFs and run them into a multiplier with the original \$S_{i}\$, then add the output. So my implementation from a program called digital is this:

Which I believe is the same, however, I am noticing some variations. I added more DFFs because I want to be able to correlate more bits. I also am not really sure if I implemented the "Sums" correctly, I also skipped the fist add from the first multiply for this reason. Some other issues I had include issues from the program. I ultimately used this program because I can take the design and get Verilog code out of it. But when I try to export as Verilog I get the error:

Can anyone help confirm if I'm on the right track with this implementation or if it is correct. It seems like the first adder is having issues but I am also unsure of what the first \$C_{i}\$ would be. In verilog I could just set it to a 0 bit but not sure how to do that in a design.