For an implemented FIR filter in Verilog, I generate filter coefficients using Python's scypi. Using its firwin-function, I receive 64-bit floating-point coefficients like:

# Everything in hz
firwin(numtaps=100,
       cutoff=1000, 
       window="hamming",
       fs=50000)
= [0.000319, 0.0007502, 0.001840, ...]

The module header of a single fir tap allows to modify its data-width.

module single_tap #(
  parameter DataWidthBits = 32,
  parameter FilterCoeff   = 32'h00000001
)(
  clk,
  resetn,
  in_data,
  out_data
);

The ADC's conversion results are 24 bit. So I suspect I will set the filter-taps data-width to 24 bits as well.

My question is: How do I have to represent the float filter coefficients as hex (or bin) in the filter to receive correct results? More specifically, I don't know if I need to scale the coefficients and how I convert them to hex (or bin) correctly.

For an implemented FIR filter in Verilog, I generate filter coefficients using Python's scypi. Using its firwin-function, I receive 64-bit floating-point coefficients like:

# Everything in hz
firwin(numtaps=100,
       cutoff=1000, 
       window="hamming",
       fs=50000)
= [0.000319, 0.0007502, 0.001840, ...]

The module header of a single fir tap allows to modify its data-width.

module single_tap #(
  parameter DataWidthBits = 32,
  parameter FilterCoeff   = 32'h00000001
)(
  clk,
  resetn,
  in_data,
  out_data
);

The ADC's conversion results are 24 bit. So I suspect I will set the filter-taps data-width to 24 bits as well.

My question is: How do I have to represent the float filter coefficients as hex (or bin) in the filter to receive correct results? More specifically, I don't know if I need to scale the coefficients and how I convert them to hex (or bin) correctly.

For the above mentioned filter, I receive a minimum value of float(0.00029975941860797253) and a maximum value of float(0.003999047325187148)

For an implemented fir filter in verilog, I generate filter coefficients using Python's scypi. Using its firwin-function, i receive 64-bit floating-point coefficients like

# Everything in hz
firwin(numtaps=100,
       cutoff=1000, 
       window="hamming",
       fs=50000)
= [0.000319, 0.0007502, 0.001840, ...]

The module header of a single fir tap allows to modify its data-width.

module single_tap #(
  parameter DataWidthBits = 32,
  parameter FilterCoeff   = 32'h00000001
)(
  clk,
  resetn,
  in_data,
  out_data
);

The ADC's conversion results are 24bit. So I suspect I will set the filter-taps data-width to 24bits aswell.

My question is: How do I have to represent the float filter coefficients as hex (or bin) in the filter to receive correct results. More specifically, I don't know if I need to scale the coefficients and how I convert them to hex (or bin) correctly.

For an implemented FIR filter in Verilog, I generate filter coefficients using Python's scypi. Using its firwin-function, I receive 64-bit floating-point coefficients like:

# Everything in hz
firwin(numtaps=100,
       cutoff=1000, 
       window="hamming",
       fs=50000)
= [0.000319, 0.0007502, 0.001840, ...]

The module header of a single fir tap allows to modify its data-width.

module single_tap #(
  parameter DataWidthBits = 32,
  parameter FilterCoeff   = 32'h00000001
)(
  clk,
  resetn,
  in_data,
  out_data
);

The ADC's conversion results are 24 bit. So I suspect I will set the filter-taps data-width to 24 bits as well.

My question is: How do I have to represent the float filter coefficients as hex (or bin) in the filter to receive correct results? More specifically, I don't know if I need to scale the coefficients and how I convert them to hex (or bin) correctly.