How do I size the coupling capacitance for a SEPIC converter?

Question

The app notes I've seen for a SEPIC converter¹ all tell me to size the coupling capacitor for ripple currents and voltages. I haven't seen one that tells me how to size the capacitance. Obviously there's some minimum; zero capacitance means no coupling, so the input has no effect on the output. To make the switching effects couple from input to output, we need enough capacitance to overwhelm any parasitic capacitances on the output side of the converter. Maybe 1000 pF should do that, I think, depending on what else is going on in the circuit. But the reference design I've inherited uses a 1 uF cap, which seems like it may be overkill for that purpose. Which makes me think there's more going on for sizing that capacitor than just overcoming parasitic capacitance.

How do I properly size the coupling capacitor in a SEPIC converter?

¹ _{For example, this Texas Instruments AN-1484 Designing A SEPIC Converter.}

Answer 1

To make the switching effects couple from input to output, we need enough capacitance to overwhelm any parasitic capacitances on the output side of the converter.

If the two inductors are coupled then a SEPIC can become a flyback converter and the capacitor is not needed. This tells you that there is no minimum value for the coupling capacitor: -

I think it's worth linking to this article where I stole the picture.

The article is a called "Power supply topology: SEPIC vs Flyback" published by Electronics Weekly.

Basically and in simple terms you don't need the capacitor if using coupled inductors but, the more capacitance you apply the more like a SEPIC converter it becomes with the various trade-offs you'll get.

Answer 2

Most of the steady state equations for a CCM SEPIC rely on voltage across \$C_c\$ being ~\$V_{\text{in}}\$, so it's best to keep the ripple voltage small compared to \$V_{\text{in}}\$. When using an electrolytic capacitor, choosing a part that could take the RMS current, pretty much makes ripple voltage across \$C_c\$ small enough. Of course, this may not be true with a ceramic part.

For parts with low ESR, maximum ripple voltage across \$C_c\$ would be less than \$\frac{I_{\text{out}}}{C_c f_{\text{pwm}}}\$. Start with 0.1 \$V_{\text{in}}\$ ripple voltage to choose a value for \$C_c\$. Here's a basic reference for designing a SEPIC, although it doesn't explicitly tell you how to choose the value of \$C_c\$.

It's interesting how, if \$C_c\$ is made small value and the output inductor is made smaller than the input inductor, and maybe a little capacitance is added across the switch, the SEPIC starts to look like a Class E converter.