I was wondering if it is possible to automatically generate a schematic from some higher-level description (CPU ==> RAM, etc) of a circuit? And whether there are tools that can do that?
6
-
1\$\begingroup\$ This is kind of done inside an FPGA or EPLD. \$\endgroup\$– Andy akaCommented Jan 4, 2017 at 14:27
-
\$\begingroup\$ Yes, from a hardware description language en.wikipedia.org/wiki/Hardware_description_language like VHDL or Verilog a netlist can be generated which is used to (automatically) make the layout of an IC (chip). This only for digital circuits. Also see: en.wikipedia.org/wiki/Processor_design . Analog circuits are manual only. \$\endgroup\$– BimpelrekkieCommented Jan 4, 2017 at 14:31
-
\$\begingroup\$ Your question isn't clear enough. You mean generate a nice, human-readable schematic that you can then print and show to your boss? This is what I understand but it seems others had a different interpretation. Please clarify. \$\endgroup\$– dimCommented Jan 4, 2017 at 14:43
-
5\$\begingroup\$ And, if my interpretation is correct, this is a duplicate of electronics.stackexchange.com/questions/272765/… and electronics.stackexchange.com/questions/18446/… \$\endgroup\$– dimCommented Jan 4, 2017 at 14:45
-
1\$\begingroup\$ Yes. For example, this handy diagram of a PCIe controller really helped me understand what was wrong. \$\endgroup\$– Simon RichterCommented Jan 4, 2017 at 14:49
|
Show 1 more comment
2 Answers
\$\begingroup\$
\$\endgroup\$
There are such tools, e.g Altera Qsys. You tell the tool which blocks you want to include (CPUs, memory, peripherals) and define a memory map. The tool then generates the system logic using the interface bus of your choice (Avalon, AMBA, etc.) Typically, some sort of include files are generated as well, to facilitate software development.
answered Jan 4, 2017 at 14:32
\$\begingroup\$
\$\endgroup\$
Some VHDL tools do offer schematic diagram generators, and they are generally appalling. They are logically correct of course, but completely ineffective as an aid to understanding.
It's not surprising when you consider how difficult it is to tell an electronics noob what constitutes a good schematic. Once you have +ve up and signals left to right, there's still plenty of scope to make a difference between ugly/useless and well-designed/useful. And that's a human you're trying to tutor, not a program you're trying to write.
In my experience, engineers only get one printout of the auto generated schematic. After that, they do their own high level block diagram in powerpoint, improve their choice of names, and then rely on the blocks being small enough to understand the VHDL.
