LDO Output Capacitor Selection and ESR Consideration

Question

For a simple application of a voltage regulator with 5V in and 3.3V out, I am looking at these three regulators.

1)AP2127K-3.3TRG1

2)MIC5504-3.3YM5-TR

3)TLV73333PDBVR

They all have different output capacitor requirements.

Regulator #1 (AP2127K-3.3TRG1) Says the following in the datasheet:

"Compatible with Low ESR Ceramic Capacitor: 1μF for CIN and COUT"

And also has this graph of stability range for an output cap of 4.7uF

To me, "Low ESR Ceramic Capacitors" means ceramic capacitors with much lower ESR than 100mOhms. What frequency is this part referring too for it's ESR ratings?

Regulator number 2 (MIC5504-3.3YM5-TR) says this in the datasheet.

"The regulator requires an output capacitor of 1uF or greater to maintain stability. The design is optimized for use with low-ESR ceramic chip capacitors. High ESR capacitors are not recommended because they may cause high-frequency oscillation."

"Stable with 1uF ceramic output capacitors"

I did not see any exact ESR ranges specified. What does this mean? "Low ESR". Regulator number 1 seems to think it's above 100mOhms.

Regulator number 3 (TLV73333PDBVR) says this in the datasheet.

"The TLV733 series is designed with a modern capacitor-free architecture to ensure stability without an input or output capacitor."

This means the regulator control loop is stable with 0 ESR caps and I can put any ceramic cap I want on there.

"However, the TLV733 series is also stable with ceramic output capacitors if an output capacitor is necessary."

Since these are all the same PCB package, I would like to provide alternate part numbers for the one I choose, but the output cap has to work with all of them.

Questions:

1) What frequencies are the datasheets referring to when they rate the ESR value? Regulator 1 and 2 seem to have different opinions. AVX Corp datasheet lists all tantalum caps ESR at 100kHz. Is this the industry standard frequency for LDO ESR ratings too?

2) I have read app notes that say not to use 0.1uF bypass caps on the output because you can end up with the pole and zero cancelling each other out and the regulator could end up unstable. But most schematics I see have one. Is this because the designer calculates what the zero and pole is or is this normally done in error?

3) Since Regulator #2 says not to use high ESR caps, does that mean regulator #1 and #2 can't use the same output cap? Since #1 would require a minimum ESR greater than the maximum ESR of #2? Even though #2 doesn't specify ESR range.

Answer 1

What frequency is this part referring too for it's ESR ratings?

and

1) What frequencies are the datasheets referring to when they rate the ESR value? Regulator 1 and 2 seem to have different opinions. AVX Corp datasheet lists all tantalum caps ESR at 100kHz. Is this the industry standard frequency for LDO ESR ratings too?

The problem with 'low ESR' is its a nebulous marketing term, if your really interested in finding what the ESR is for the capacitor, the frequency and impedance for the capacitor must be known. Usually that means actually digging through the capacitors datasheet or requesting manufacturer impedance information (by request I mead looking for the information on their website)

Usually they mean 10kHz to 100kHz but this can vary from LDO to LDO there is no industry standard. Its from the voltage control loop and it varies from design to design.

So from a design perspective this means digging through the datasheet and finding the ripple and the ESR of the capacitor that they used and ensuring that the ESR is lower than that value. So I would find the lowest ESR capacitor that is available on the market and throw that in your design. How do you do that? compare some capacitors and find the one that has the best impedance curve or a lower impedance curve than the capacitors recommended.

From ESR stability and the LDO regulator

A capacitor ESR graph looks like the one below, at some manufacturers you can compare these values. or find them in datasheets to get a feel for ESR.

2) I have read app notes that say not to use 0.1uF bypass caps on the output because you can end up with the pole and zero cancelling each other out and the regulator could end up unstable. But most schematics I see have one. Is this because the designer calculates what the zero and pole is or is this normally done in error?

Remember that instability is only a problem if you have transient loads and at the frequency range of interest. Instead of worrying so much about ESR, you should be worried about ripple and under what conditions this can happen. If you do have transient loads (especially transient from 1kHz to 1Mhz see above plot) and you are concerned about the ripple then you do need to worry about the ESR. If ripple isn't a concern then don't worry about it.

The manufacture is trying to guarantee their ripple specs, they don't want engineers telling them that their products are defective because there is too much ripple at higher frequencies.

If you really want to know where the pole comes from:

The pole is at higher frequencies (as shown in the plot above, which applies to most regulators but not all). Stated another way, the system must have sufficient phase margin, i.e., the amount of phase shift remaining until 360° degree when the gain is at 0 dB. Since each pole contributes 90° of phase shift and 20dB/decade (or –1) rolloff in gain, a three-pole, high gain system requires compensation in order to be stable. A regulator is nconditionally stable (i.e., has sufficient phase margin) if the open loop gain curve rolls off at 20dB/decade (i.e., like a single polesystem) before crosses 0 dB. The most common method of compensation is to insert a zero inthe system to cancel the phase shift and rolloff of one of the poles. Since an LDO already requires an output capacitor for normal operation, using the output capacitor’s ESR is typically the simplest and least expensive method for generating this zero.

Also From ESR stability and the LDO regulator

3) Since Regulator #2 says not to use high ESR caps, does that mean regulator #1 and #2 can't use the same output cap? Since #1 would require a minimum ESR greater than the maximum ESR of #2? Even though 2 doesn't specify ESR range.

It might, if they have different types of control loops then you might have a problem specifying the same capacitor. Make life simpler for yourself, sample some LDO's throw them on the board in question (with the same capacitor) and measure the ripple under operation. Use a capacitor with a reasonably low ESR

Answer 2

I'm unable to answer all questions directly, but I suggest to:

• stick to the output capacitor requirements given in the datasheet of your specific LDO.
• test your design with load transients and check that the output voltage remains stable.
• for capacitor ESR, take the minimum of the capacitor ESR graph to err on the safe side.

I figured this out using a similar LDO as you, the AP2210.

In the datasheet, multiple graphs for the stability range are presented for different output capacitances.

Further, this regulator has an additional pin where you can connect a noise bypass capacitor. According to the datasheet adding this capacitor results "in a significant reduction in output noise". However, the datasheet also notes that "the ESR stable area will be narrowed" by this bypass capacitor without providing any specifics.

I added this noise bypass capacitor (100 pF) and ended up with an oscillating output voltage:

Obviously, my design was now outside the stable area.

As the LDO was powering a microcontroller, noise was not important so I removed the noise bypass capacitor and got a stable output voltage: